5G产业报告-PDF版

【研报】半导体行业颗粒硅：多晶硅技术的再次腾飞-20201203（14页）.pdf

2020年年12月月3日日 颗粒硅：多晶硅技术的再次腾飞颗粒硅：多晶硅技术的再次腾飞 证券研究报告证券研究报告 （优于大市，维持优于大市，维持） 概要概要 1.颗粒硅简介：颗粒硅简介：硅烷法生产的颗.

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【公司研究】2020年三安光电企业加速布局第三代化合物半导体深度研究报告（17页）.pdf

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2020-12-03 17页 5星级

【研报】2020年分立器件行业功率半导体市场发展分析研究报告（19页）.pdf

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2020-12-02 19页 5星级

NXP半导体公司：2020年公司概述（英文版）（21页）.pdf

经验VXP资深员工，在销售和市场营销、产品定义、开发和管理方面有25年以上的工作经验。连续性自2009年起成为恩智浦执行团队的成员，并在2015年成为恩智浦与飞思卡尔半导体合并的关键领导者。自2018.

2020-12-01 21页 5星级

云岫资本：2020年中国半导体行业投资解读（20页）.pdf

芯片产能紧张，制造封测进入新一轮涨价周期。关注“卡脖子”领域和大芯片，半导体设计进入深水区。半导体设备和材料行业持续景气。2020年半导体材料获得融资项目超过40个总融资金额或超120亿人民币。202.

2020-12-01 20页 5星级

OMDIA：2020光纤网络技术咨询报告（英文版）（26页）.pdf

区域网络硬件收入北美是唯一一个在 20 年第一季度同比增长的地区由ICP和5G基础设施驱动. 与 1Q19QoQseasonality 相比，1020 年全球仅下降 3%. 迄今为止，covID-19.

2020-12-01 26页 5星级

半导体行业研究：2020-2021年投资展望从应用到行业的全面复苏（41页）.pdf

非美核芯设计替代的赢家自从美国 Trump 政府宣布将华为及其 68 家子公司，中科曙光，天津海光先进技术，成都海光集成，成都海光微电子，海康，大华，科大讯飞，旷视，商汤，厦门美亚柏科，依图，颐信科技.

2020-12-01 41页 5星级

【研报】2020年电子行业第三代半导体材料分析研究报告（27页）.pdf

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2020-12-01 27页 5星级

【研报】2020年半导体行业分析研究报告-RCEP协定对中国先进制造业的影响分析（37页）.pdf

Table_Info4 Nomura | 半导体 2020.11.28 Table_Info4 请务必阅读报告正文后各项声明请务必阅读报告正文后各项声明 3 正文目录正文目录 RCEP 释放政策红利.

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【研报】电子行业十四五规划半导体专题：政策助力半导体产业实现跨越式发展-20201116（28页）.pdf

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2020-11-19 28页 5星级

【研报】半导体材料行业深度专题：靶材国产替代大势十倍空间可期-20201116（84页）.pdf

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2020-11-18 84页 5星级

【公司研究】华润微-特色工艺平台系列报告（三）：全面布局第三代半导体产业链构筑第二增长曲线-20201109（21页）.pdf

华润微公司作为特色工艺超级平台，目前已实现国内首条 6 英寸 SiC 生产线的量产，有望全 面布局包括 SiC 和 GaN 在内的第三代半导体产业链，构筑第二增长曲线。特色工艺平台持续加深布局，驱动 .

2020-11-10 21页 5星级

【研报】半导体行业：电子年度策略报告否极泰来-20201106（115页）.pdf

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2020-11-09 115页 5星级

【研报】电子行业：半导体三大周期再度共振开启上行周期-20201102（59页）.pdf

请仔细阅读本报告末页声明请仔细阅读本报告末页声明 证券研究报告 | 行业深度 2020 年 11 月 02 日 电子电子 半导体半导体：三大周期再度共振，开启上行周期三大周期再度共振，开启上行周期 .

2020-11-03 59页 5星级

【研报】半导体行业：APU赛道分析-20201101（113页）.pdf

APU赛道分析赛道分析 首席电子分析师: 贺茂飞 执业证书编号: S0020520060001 e-mail ： 证券研究报告证券研究报告 20202020年年1111月月0101日日 请务必阅读正文.

2020-11-02 113页 5星级

【研报】电子行业半导体系列研究之十一：日本JSR全球ArF光刻胶龙头-20201030（18页）.pdf

Table_Info1 半导体半导体 电子电子 TABLE_TITLE 日本日本 JSR：全球：全球 ArF 光刻胶龙头光刻胶龙头 半导体系列研究之十一 证券研究报告证券研究报告 2020 年 10.

2020-11-02 18页 5星级

2020年基于功率半导体碳化硅的可靠性报告 - 英飞凌（英文版）（45页）.pdf

v1.0 How Infineon controls and assures the reliability of SiC based power semiconductors Whitepaper 07-2020 How Infineon controls and assures the reliability of SiC based power semiconductors 2 07-2020 Table of contents 1 Introduction 3 2 Why do SiC based devices require some additional and different reliability tests compared to Si based devices? 4 3 Gate-oxide reliability of industrial SiC MOSFETs FIT rates and lifetime 5 3.1 Introduction to gate oxide reliability for SiC MOSFETs 5 3.2 Basic aspects of SiC MOSFET gate-oxide reliability screening 5 3.3 Stress tests for extrinsic gate-oxide reliability evaluation 7 3.3.1 Marathon stress test 7 3.3.2 Gate voltage step-stress test 9 3.4 Conclusions 10 4 Gate-oxide reliability of industrial SiC MOSFETs Bias Temperature Instabilities (BTI) 11 4.1 Parameter variations of SiC MOSFETs under constant gate bias conditions (DC BTI) 11 4.1.1 Introduction to DC BTI 11 4.1.2 Measuring DC BTI in SiC power devices 12 4.1.3 Comparison of DC BTI in SiC and Si power MOSFETs 13 4.2 Parameter variations of SiC MOSFETs under real world application gate switching operating conditions (AC BTI) 16 4.2.1 Introduction 16 4.2.2 AC BTI modelling 17 4.2.3 Basic characteristics of AC BTI 18 5 Silicon carbide cosmic ray robustness 22 6 Short circuit ruggedness of CoolSiC MOSFETs 26 7 SiC body diode bipolar degradation 28 7.1 Mechanism 28 7.2 Effects in the application 29 7.3 CoolSiC MOSFET strategy to eliminate the risk 29 8 Qualification at the product level 30 8.1 Testing beyond todays standards according to real world mission profiles 30 8.2 AC-HTC test procedure 33 8.3 Power cycling seconds 34 8.4 Long-term application tests 35 9 Automotive qualification: an approach beyond the standard 36 9.1 Higher field reliability for automotive SiC customers 38 9.2 No compromises on robustness against humidity for automotive parts 39 10 Industry standards for SiC device reliability and qualification 41 How Infineon controls and assures the reliability of SiC based power semiconductors 3 07-2020 1 Introduction Infineons CoolSiC trench based silicon carbide power MOSFETs represent a dramatic improvement in power conversion switching device Figure Of Merit (FOM) values with outstanding system performance. This enables higher efficiency, power density and reduced system cost in many applications. This technology can also be considered as being an enabler for new applications and topologies. However, as with all new technologies, it is essential that a thorough technology development and product qualification procedure is followed. Only in this way can design lifetime and quality requirements for power conversion systems be achieved. Despite the similarities to silicon, e.g. the vertical device structures, the presence of a native oxide like SiO2 or the majority of processing steps, there are still important differences related to the material properties itself and the operating modes of these new power devices. As these differences are substantial, their impact on the operation in the final application and on the required development and reliability qualification processes must be carefully considered. This paper describes the major steps in the release process that Infineon has used to successfully qualify CoolSiC technology and products. Key failure mechanisms are described, and the means to ensure safe and reliable operation in a wide variety of applications are provided. Through this approach, many risks our customers would otherwise encounter are avoided and a safe path to the reliable use of Infineon CoolSiC technology is provided. This publication also holds tutorial value to engineers with an interest in better understanding silicon carbide related reliability. How Infineon controls and assures the reliability of SiC based power semiconductors 4 07-2020 2 Why do SiC based devices require some additional and different reliability tests compared to Si based devices? One of the success factors of implementing SiC as a power device material is the chance to adopt many of the well known device concepts and processing technologies from silicon. Among those are the basic device designs like vertical Schottky diodes or vertical power MOSFETs (after some detours via JFETs and BJTs as alternative structures). Thus, many of the procedures used to verify the long term stability of silicon devices could be transferred to SiC. Nevertheless a deeper analysis has shown that SiC based devices require some additional and different reliability tests compared to Si based devices. The major items which turned out to be relevant are the following: The material itself with its specific defect structures, anisotropies, mechanical and thermal properties etc. The larger bandgap with its implications on the density and dynamics of interface traps in MOS based devices Up to about 10 x higher electrical fields in operation within the material itself and at the outside interfaces, e.g. device edges (including new edge termination designs), plus its impact on oxide lifetime New operating modes where high voltage operation (VDS 1000 V) and fast switching ( 50 V/ns) are combined The listed items may have an influence on nearly all established qualification tests. Power cycling second tests will lead to different results due to different mechanical properties. Contrary to silicon based power devices the setup of oxide reliability tests for SiC have to also cover stability in blocking mode. Furthermore, for many existing qualification standards that specify accelerated tests, models are used to extrapolate the test data and correlate it to real world application conditions. These model parameters need to be verified for their application and accuracy with respect to SiC. Infineon has intensely analyzed all of these items over the last 25 years during the development and production of SiC based power devices. New tests have been developed to address different operating modes not seen by silicon power semiconductors and other tests have been modified to take into account SiC specific requirements. It is important to emphasize, that key parts of the characterization and validation scheme are based on a mission profile based stress analysis. This was done in order to assess the critical operating conditions for SiC devices and to understand new potential failure mechanisms. The details are described in the following chapters. How Infineon controls and assures the reliability of SiC based power semiconductors 5 07-2020 3 Gate-oxide reliability of industrial SiC MOSFETs FIT rates and lifetime 3.1 Introduction to gate oxide reliability for SiC MOSFETs High numbers of early gate-oxide failures have hampered the commercialization of SiC MOSFETs for many years, and provoked skepticism whether SiC MOS switches would ever be as reliable as their Si counterparts. During the last decade, SiC technology has substantially matured and SiC MOS devices have exhibited gradual improvements in gate-oxide reliability. This has opened the door for their successful introduction into the mass market. In the field of gate-oxide reliability, there is a lot of expertise that can be reused from Si technology. For instance, it was shown that the physical breakdown strength of SiO2 on SiC is similar, if not identical, to SiO2 on Si 1. This means that the overall breakdown stability of SiO2 fabricated on SiC is as good as SiO2 fabricated on Si. The shortcoming in gate-oxide reliability of SiC MOSFETs with respect to Si MOSFETs is due to “extrinsic” defects. Extrinsic defects are tiny distortions in the gate-oxide, which act as local oxide thinning, cf. Figure 1. Figure 1 Schematic representation of extrinsic defects in SiO2. Extrinsic defects can be physical oxide thinning due to, for instance, a distorted oxide on top of an EPI/substrate defect or electrical oxide thinning caused by a degraded dielectric field strength due to inclusions of metallic impurities, particles or porosity 2. Such distortions may originate from EPI or substrate defects 2, metallic impurities, particles or other extrinsic inclusions in the gate-oxide incorporated during device fabrication. 3.2 Basic aspects of SiC MOSFET gate-oxide reliability screening At the end of processing, gate-oxides fabricated on SiC have typically a much higher early failure probability because they exhibit higher numbers of extrinsic defects, cf. Figure 2. How Infineon controls and assures the reliability of SiC based power semiconductors 6 07-2020 Figure 2 Schematic representation of the extrinsic and intrinsic Weibull distributions for SiC MOSFETs and Si MOSFETs having the same oxide thickness and area. F depicts the cumulative failure probability, t the time. Due to a higher electrical defect density, SiC MOSFETs exhibit 3-4 orders of magnitude higher extrinsic defect densities in the gate- oxide. The chip lifetime is the time the device has to survive in the application under normal use conditions. To make SiC MOSFETs as reliable as their Si counterparts, the gate-oxide defect density has to be minimized during processing. Additionally, innovative screening techniques, to identify and eliminate potentially weak devices, e.g. in the electrical end test, have to be developed. The screening of weak devices in the end test is typically done by subjecting each device to a high gate-voltage stress pulse with defined amplitude and time 3 4. The stress pulse is designed to identify devices with critical extrinsic defects while devices without extrinsic defects or with only non-critical extrinsic defects survive. The remaining surviving, screened, population shows a significantly improved gate-oxide reliability 5. The enabler for a fast and efficient gate-voltage screening is a much thicker bulk-oxide layer than what is typically needed to fulfill intrinsic lifetime-targets. The thicker bulk-oxide layer allows the use of screening voltages much higher than the typical device use-voltage without degradation of non-defective devices which are passing the screening test. The higher the screening voltage to the use-voltage ratio, the more efficient the electrical screening 6. By eliminating defective devices in the end test a potential reliability issue for the customer is converted to a minor yield loss for the device manufacturer. SiC MOSFETs that pass our screening test show the same excellent level of gate-oxide reliability as Si MOSFETs or IGBTs 7. The downside of a thicker bulk-oxide layer is a slightly higher MOS channel resistance. The MOS channel resistance is directly proportional to the gate-oxide thickness and can be a major portion of the total on-resistance, in particular, for devices of lower voltage classes that provide a comparatively small drift-zone resistance. Ultimately, high screening efficiency, and hence excellent gate-oxide reliability of SiC MOSFETs, is not entirely for free, but comes at the cost of a slightly increased on-resistance. This design trade-off between reliability and performance is inevitable, however, it is possible to take advantage of the fact that on-resistance and gate oxide reliability show a different dependence on bulk oxide thickness. SiC MOSFET () Si MOSFET -6 -2 intrinsic branch extrinsic branch chip lifetime uncritical critical (1 ) How Infineon controls and assures the reliability of SiC based power semiconductors 7 07-2020 While gate oxide reliability improves exponentially with oxide thickness, the on-resistance increase is only linear. At elevated temperatures, where the drift-zone resistance is more pronounced, the performance penalty is even smaller in relative numbers. To summarize, by sacrificing just a little performance by using a thicker bulk-oxide layer leads to a strong gain in reliability. Infineon decided, from the beginning, to use a Trench based MOSFET technology. The reason for this is that trench based devices, compared to planar devices, have significantly higher channel conductivities at low electric fields across the gate oxide during on-state of a MOSFET as the penalty of a thick oxide layer. A not very attractive alternative to gate voltage screening at high screening voltages and room temperature is the classic burn-in test. During burn-in devices are typically stressed at somewhat lower gate voltages and elevated temperatures for much longer times. This approach has several disadvantages. A burn-in is time-consuming, costly, and may cause severe drift of threshold voltage and on-resistance due to long-lasting gate stress at high bias and high temperature, which is known to trigger bias temperature instabilities 8. 3.3 Stress tests for extrinsic gate-oxide reliability evaluation To make reliable predictions about failure probabilities under normal device operation conditions, it is mandatory to perform stress tests that explore the early breakdown regime of device failure 9. Stress tests aiming to explore the oxide wear-out regime, such as highly accelerated Time-Dependent- Dielectric-Breakdown (TDDB) tests which are typically performed only on a small number of samples, are not appropriate to study failures that may happen during normal device operation (voltage, temperature) within typical chip lifetimes. To overcome this problem, Infineon developed two different stress test approaches to verify the screening and thereby the gate oxide reliability for all devices. 3.3.1 Marathon stress test A common approach to study extrinsic failures is to stress devices as close as possible to the real world application conditions and at the same time test large numbers of samples. Large sample sizes are required because extrinsic failures are usually rare, in particular, after electrical screening. For this purpose, we have developed a new kind of test procedure, which we call the “marathon stress test” 5. In this test, thousands of devices are stressed in parallel in a parameter range close to operating conditions and comparable to typical burn-in conditions. However, contrary to burn-in, we use much longer stress times (100 days) in order to increase the probability to find extrinsic failures. To manage the large sample quantities required for the marathon stress test, we have developed a special test setup in which we put multiple devices in one package, many packages on one stress board and several stress boards into one furnace. Multiple furnaces are can be operated in parallel. In a case study, we have performed three independent marathon test runs on three sample groups of electrically screened devices with different extrinsic defect densities. The three groups roughly align with the progress made during the device development phase, namely group 1 corresponds to the initial stage of oxide process development while group 3 represents the technology status shortly before How Infineon controls and assu

2020-11-01 45页 5星级

【研报】全球新经济产业专题：招兵买马后半导体产业的三分天下英伟达、AMD、英特尔-20201023（18页）.pdf

证券 证券研究报告 请务必阅读正文之后的免责条款 招兵买马后，半导体产业的三分天下：英伟 招兵买马后，半导体产业的三分天下：英伟 达、达、AMD、英特尔、英特尔 全球新经济产业专题2020.10.23.

2020-10-26 18页 5星级

【研报】半导体产品与半导体设备行业：国内模拟芯片行业黄金级赛道白金级选手-20201020（22页）.pdf

请务必阅读正文之后的信息披露和法律声明 Table_MainInfo 行业研究/信息设备/半导体产品与半导体设备 证券研究报告 行业深度报告行业深度报告 2020 年 10 月 20 日 Table.

2020-10-21 22页 5星级

【研报】电子行业：功率半导体需求旺盛涨价潮与国产替代驱动业绩增长-20201013（38页）.pdf

东方证券股份有限公司经相关主管机关核准具备证券投资咨询业务资格，据此开展发布证券研究报告业务。 东方证券股份有限公司及其关联机构在法律许可的范围内正在或将要与本研究报告所分析的企业发展业务关系。因此.

2020-10-14 38页 5星级