SESSION 36 Ultra-High-Density D2D.pdf

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1、ISSCC 2025SESSION 36 Ultra-High-Density D2D and High-Performance Optical Transceivers36.1:A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating 2025 IEEE International Solid-State Circuits Conference1 of 29A 32Gb/s 10.5Tb/s/mm 0.6pJ

2、/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock GatingMu-Shan Lin1,Chien-Chun Tsai1,Shenggao Li1,Wei-Chih Chen1,Wen-Hung Huang1,Yu-Chi Chen1,Yu-Jie Huang1,Alan Drake1,Chin-Hua Wen1,Paul Ranucci1,Hsin-Hung Kuo1,Aidong Yin1,Shu-Chun Yang1,Farsheed Mahmoudi1,Han

3、-Tzung Ke1,Chao-Chieh Li1,Nai-Chen Cheng1,Jimmy Wang1,Kevin Lin1,Harry Liao1,Jie-Ren Huang1,Meng-Hsuan Wu1,Kenny Cheng-Hsiang Hsieh1,Nicholas Amatruda2,William Polanco2,David King2,Todd Basso2,Anwar Kashem2TSMC1/AMD236.1:A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featur

4、ing Matched-Delay for Dynamic Clock Gating 2025 IEEE International Solid-State Circuits Conference2 of 29Outline Motivation Design Scope Overview Die-to-Die Interface ArchitectureClock ArchitectureTransmitter Circuit ArchitectureReceiver Circuit Architecture Testing Strategy&PI Analysis Measurement

5、Results Comparison&Conclusion36.1:A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating 2025 IEEE International Solid-State Circuits Conference3 of 29Die-to-Die Interface Performance:FoM(BW Density/Energy Efficiency)vs.Interconnect

6、DistanceUCIe advanced package has the best FoM around 2mm but demands a high current density100100010000100000110BW Density/Energy Efficiency(Gb/s/mm)/(pJ/bit)Interconnect Distance(mm)2 VLSI233 ISSCC24UCIe SPUCIe AP1 ISSCC234 VLSI2436.1:A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interfa