Session 16Highlighted Chip Releases_ Digital and Machine Learning Processors.pdf

《Session 16Highlighted Chip Releases_ Digital and Machine Learning Processors.pdf》由会员分享，可在线阅读，更多相关《Session 16Highlighted Chip Releases_ Digital and Machine Learning Processors.pdf（14页珍藏版）》请在三个皮匠报告上搜索。

1、Session 16 Overview:Highlighted Chip Releases:Digital and Machine Learning Processors INVITED INDUSTRY SESSION Thi s sessi on hi ghli ghts recent,producti zed advancements i n di gi tal processors and systems for AI accelerati on and hi gh-performance networki ng.Key i nnovati ons i nclude novel arc

2、hi tectures for AI processi ng,sophi sti cated memory archi tectures,and advanced swi tch chi p desi gns.The work presented i n thi s sessi on demonstrates si gni ficant i mprovements i n AI capabi li ti es,power effici ency,and scalabi li ty across vari ous appli cati ons,from mobi le devi ces to d

3、ata centers.The sessi on provi des an overvi ew of current state-of-the-art hardware soluti ons addressi ng the demands of modern computi ng workloads.Session Chair:Ali ci a Kli nefelter NVI DI A,Durham,NC Session Co-Chair:Vi vek De I ntel,Hi llsboro,OR 280 2025 I EEE I nternati onal Soli d-State Ci

4、 rcui ts ConferenceISSCC 2025/SESSION 16/HIGHLIGHTED CHIP RELEASES/OVERVIEW979-8-3315-4101-9/25/$31.00 2025 I EEE2:20 PM 16.3 An On-Device Generat ive AI Focused Neural Processing Unit in 4nm Flagship Mobile SoC wit h Fan-Out Wafer-Level Package Jun-Seok Park,Samsung Electroni cs,Hwaseong,Korea I n

5、I nvi ted Paper 16.3,Samsung i ntroduces thei r Exynos 2400 SoC,used i n the Galaxy S24 smartphone.I t features a 4nm EUV process and supports on-devi ce AI wi th a heterogeneous NPU archi tecture consi sti ng of vector engi nes and two types of tensor engi nes.The 4nm SoC achi eves i mproved AI per

6、formance through better heat di ssi pati on usi ng fan-out wafer level packagi ng,wi th the NPU occupyi ng 12mm and operati ng at 0.55 to 0.83V and 533 to 1196MHz.2:45 PM 16.4 SambaNova SN40L:A 5nm 2.5D Dat aflow Accelerat or wit h Three Memory Tiers for Trillion Paramet er AI Raghu Prabhakar,SambaN