Session 18Noise-Shaping and SAR-Based ADCs.pdf

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1、Session 18 Overview:Noise-Shaping and SAR-Based ADCs DATA CONVERTER SUBCOMMITTEEThis session presents eight ADCs where noise-shaping techniques and SAR/Pipe-SAR structures are well exploited.These papers are sorted in ascending order of speed.With 170dB.The last paper is a cryo-CMOS CI-SAR ADC with

2、a 4fF input capacitance.Session Co-Chair:Pieter Harpe Eindhoven University of Technology Eindhoven,The NetherlandsSession Chair:Xiyuan Tang Peking University,Beijing,China 304 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 18/NOISE-SHAPING AND SAR-BASED ADCS/OVERVIEW979-8-

3、3315-4101-9/25/$31.00 2025 IEEE1:30 PM 18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMS in 1kHz BW Xuanhao Zhang,University of Electronic Science and Technology of China,Chengdu,China In Paper 18.1,UESTC presents a fully dynamic NS-SAR ADC achieving 120.6dB SNDR and 132

4、.5dB SFDR in 1kHz BW,resulting in 189.2dB FoMS.The performance is enabled by predict and skip,hybrid mismatch shaping,system-level chopping,and FIA.1:55 PM 18.2 A 12.2W 99.6dB-SNDR 184.8dB-FOMS DT Zoom PPD M with Gain-Embedded Bootstrapped Sampler Yaohui Luan,Peking University,Beijing,China In Paper

5、 18.2,Peking University introduces a Gain-Embedded Bootstrapped Sampler input stage adopted in zoom pseudo-pseudo-differential ADC.This ADC achieves 99.6dB SNDR over 4kHz bandwidth and a FoMS of 184.8dB.2:20 PM 18.3 A 93.3dB SNDR,180.4dB FoMS Calibration-Free Noise-Shaping Pipelined-SAR ADC with Cro

6、ss-Stage Gain-Mismatch-Error-Shaping Technique and Negative-R-Assisted Residue Integrator Jihang Gao,Peking University,Beijing,China In Paper 18.3,Peking University proposes a calibration-free pipelined-SAR ADC with cross-stage gain-mismatch error shaping.Inherently preserving residue voltage for no