SESSION 37 Design-Technology Optimization and Digital Accelerators.pdf

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1、ISSCC 2025SESSION 37 Design-Technology Optimization and Digital Accelerators37.1:IBM Telum II processor design-technology co-optimizations for power,performance,area,and reliability 2025 IEEE International Solid-State Circuits Conference1 of 21IBM Telum IIprocessor design-technology co-optimizations

2、 for power,performance,area,and reliabilityDavid Wolpert1,Gerry Strevig2,Chris Berry1,Leon Sigal3,Bill Huott1,MarkCichanowski2,Matthias Pflanz4,Tobias Werner4,Philipp Salz4,Nick Jing1,Michael Romain1,Iris Leefken4,Richard Serton1,Rajesh Veerabhadraiah5,Dureseti Chidambarrao3,Robert Arelt1,Matt Angya

3、l1,Ben Trombley1,Arvind Haran2,Stefan Hougardy6,Ben Klotz6,Rahul Rao51IBM Poughkeepsie,NY,2IBM Austin,TX,3IBM Yorktown Heights,NY,4IBM Bblingen,Germany,5IBM Bangalore,India,6University of Bonn,Bonn,Germany37.1:IBM Telum II processor design-technology co-optimizations for power,performance,area,and r

4、eliability 2025 IEEE International Solid-State Circuits Conference2 of 21Outline Design-Technology Co-Optimization(DTCO)Technology optimizationsEnhanced library design Multiple BEOL images in both IP and synthesized blocks DFM+Design optimizationsParticle-aware latch placementLow-power latches and l

5、ocal clock buffers Chip impacts37.1:IBM Telum II processor design-technology co-optimizations for power,performance,area,and reliability 2025 IEEE International Solid-State Circuits Conference3 of 21Telum IIOverview Samsung 5 nm technology 8x 5.5 GHz cores 10 x 36 MB L2 caches3.6ns access352 GB/s ri

6、ng360 MB virtual L3(chip)2.88 GB virtual L4(drawer)On-die data processing unit Enhanced AI&security unitsFor more chip details,see Streviget al.ISSCC25,paper 2.237.1:IBM Telum II processor design-technology co-optimizations for power,performance,area,and reliability 2025 IEEE International Solid-Sta