Session 14Compute-in-Memory.pdf

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1、Session 14 Overview:Compute-in-Memory MEMORY SUBCOMMITTEEMemory access has been a major system-performance and energy-consumption bottleneck for traditional von Neumann system architectures.Compute-in-memory(CI M)architectures eliminate this bottleneck by integrating compute operations into the memo

2、ry array,to reduce memory access latency and data movement overhead.I nnovations in CI M design continue to improve energy and area efficiencies while maintaining overall AI network accuracy.This session includes 7 papers showcasing the latest developments in gain-cell,SRAM,and non-volatile CI M.Fea

3、tured innovations include the 1st demonstration of a microscaling data format and STT-MRAM based Bayesian neural network.Session Chair:Saekyu Lee EnCharge AI,Denver,COSession Co-Chair:Xueqing Li Tsinghua University,Beijing,China 248 2025 I EEE I nternational Solid-State Circuits ConferenceISSCC 2025

4、/SESSION 14/COMPUTE-IN-MEMORY/OVERVIEW979-8-3315-4101-9/25/$31.00 2025 I EEE8:00 AM 14.1 A 22nm 104.5TOPS/W -NMC-IMC Het erogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Net works De-Qi You,National Tsing Hua University,Hsinchu,Taiwan I n Paper 14.1,National Tsing Hua University and

5、TSMC present an STT-MRAM CI M macro for noise-tolerant Bayesian neural networks with a heterogeneous in-and near-memory MAC structure.The 22nm macro achieves 104.5TOPS/W with a 0.03%accuracy loss for CI FAR-100.8:25 AM 14.2 A 16nm 216kb,188.4TOPS/W and 133.5TFLOPS/W Microscaling Mult i-Mode Gain-Cel

6、l CIM Macro Edge-AI Devices Win-San Khwa,TSMC Corporate Research,Hsinchu,Taiwan I n Paper 14.2,TSMC and National Tsing Hua University demonstrate the first CI M macro demonstrating the microscaling data format;achieving 133.5TFLPOS/W in a 16nm process.8:50 AM 14.3 A 28nm 17.83-t o-62.84TFLOPS/W Broa