RISC-V欧洲峰会2025（RISC-V Summit Europe 2025）嘉宾演讲PPT合集（共60套打包）

更新时间：2025-11-04 报告数量：60份

RISC-V欧洲峰会2025嘉宾演讲PPT合集

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RISC-V欧洲峰会2025嘉宾演讲PPT合集

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- RISC-V欧洲峰会2025嘉宾演讲PPT合集
  - 欧洲半导体战略中的开源芯片设计.pdf
  - 迈向首款采用自动化端到端形式化测试的 RISC-V 芯片.pdf
  - 在威龙V2 Thunderhill FPGA平台上运行数据中心和AI推理应用程序.pdf
  - 泰雷兹开源硬件案例：动机及近期里程碑（基于 CVA6）.pdf
  - 对 CHERI 处理器进行全面的安全验证.pdf
  - 借助 RISC-V 生态系统实现规模化发展.pdf
  - 基于 RISC-V 的 FPGA GPGPU：一种具有竞争力的科学计算方法.pdf
  - 利用嵌入式功能监视器增强 RISC-V SoC 的调试和优化.pdf
  - 内存池类型：RISC-V 多核集群中的多功能性和专业化之间.pdf
  - RISE 项目：推进 RISC-V 软件.pdf
  - 挑战已接受：面向 RISCV64 生态系统的 Python 打包基础设施.pdf
  - 在 RISC-V 中实现运行时可配置字节序：挑战与解决方案.pdf
  - 通过在 IREE 中启用 RISC-V 微内核支持来加速 GenAI 工作负载.pdf
  - 用于后量子密码的基于 RISC-V 的加速器.pdf
  - 对欧洲嵌入式处理器主权的贡献.pdf
  - 基于云的 RISC-V 服务器：我们如何以及为何构建它们以及您如何使用它们.pdf
  - 利用高效软件解码器释放 RISC-V E-Trace 的强大功能.pdf
  - 利用 Andes 矩阵乘法 (AMM) 和 RISC-V 向量 (RVV) 扩展加速 AI 模型：从 CNN 到 LLM.pdf
  - 从ISA到产业界：加速技术进步和RISC-V在2025年的普及应用.pdf
  - RVA23 规范在推进 RISC-V 生态系统中的重要性.pdf
  - RISC-V系统的高效调试和跟踪：一种硬件软件协同设计方法.pdf
  - RISC-V 片上调试和跟踪解决方案：Tessent UltraSight-V.pdf
  - openEuler for RISC-V Servers： Challenges & Roadmap.pdf
  - Codasip有什么新内容？.pdf
  - 让 RISC-V 走向市场：形式化验证的经济意义.pdf
  - 实时追踪：简化嵌入式系统开发和验证的关键.pdf
  - 利用人工智能代理革新 RISC-V 芯片设计.pdf
  - 面向开源和自动化性能表征硬件.pdf
  - XiangShan KMHv2：一款开源 RISC-V 内核主频大于 15GHz适用于 SPECCPU2006.pdf
  - 主权、独立、创新：CEA 七年 RISC-V 软硬件协同设计经验.pdf
  - 真实系统真实应用-数据中心高性能 RISC-V 的下一个篇章.pdf
  - RISC-V：高性能计算的未来动力？.pdf
  - RISC-V嵌入式内核中GPSA保护的提前生成.pdf
  - RISC-V异构编程范式：原子IO入队（AIOE）扩展和虚拟化AIOE.pdf
  - 扩展开放计算：RISC-V、Chiplets 以及人工智能和机器人技术的未来.pdf
  - 借助 Andes 进入 RISC-V AI 时代.pdf
  - RISC-V ISA 扩展及其在超维计算中的硬件加速.pdf
  - 安全的软件融合：汽车和工业设计如何消除界限并创造机遇.pdf
  - RISC-V：空间计算的新轨道.pdf
  - LLVM中RISC-V Vector代码生成功能的改进.pdf
  - 助力 RISC-V 进入下一阶段：产品创新和可扩展解决方案.pdf
  - RISC-V 开放设计以及对硬件安全研究和开发活动的贡献.pdf
  - 突破绩效瓶颈.pdf
  - Akeana 利用其强大的历史传承提供最广泛的知识产权组合.pdf
  - 利用 RISC-V 跟踪标准实现高效的错误修复和性能分析.pdf
  - Monte Cimone v2：RISC-V 高性能计算机之路.pdf
  - 从开放硅到主权超级计算：EuroHPC 对 RISC-V 的愿景.pdf
  - 定制化硅芯片势在必行：应对制造和供应链的现实挑战.pdf
  - Chips JU 与未来汽车——RISC V 视角.pdf
  - 利用 SOCRATES 平台自动生成容错 SoC.pdf
  - Semidynamics 重新定义了 NPU 芯片架构打造出超强 AI 能力实现零延迟.pdf
  - VASCO：基于FD-SOI的网络安全ASIC测试平台.pdf
  - RISC-V联盟状况.pdf
  - RISC-V 的发展势头依然强劲.pdf
  - RISC-V 高级中断架构的实时扩展.pdf
  - openEuler 的 LLVM 并行宇宙项目：我们从 openEuler RISC-V 中学到了什么.pdf
  - OpenTitan Integrated：面向大型SoC的RISC-V开源硅信任根.pdf
  - Flex-RV：全球首款非硅基 RISC-V 微处理器.pdf
  - CVA6S+：具有高吞吐量内存架构的超标量 RISC-V 内核.pdf
  - AArch64 和 RISC-V 的 GCC 代码生成器对比分析.pdf

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资源包简介：

1、RISC-V Summit Europe 2025Stefan WallentowitzRISC-V Summit Europe May 15,2025Open Source Open Source Chip Design in Chip Design in the European the European Semiconductor Semiconductor StrategyStrateg。

2、 Axiomise Limited 2025.All rights reserved.Getting towards first-time RISC-V silicon with automated end-to-end formalDr.Ashish Darbari,Axiomise Axiomise Limited 2025.All rights reserved.Accelerating 。

3、Real Systems.Real Traction.Bringing High-Performance RISC-V Platforms to LifeBalaji Baktha,CEO,Ventana Micro SystemsRISC-V Europe Summit,Paris 2025Delivers a Full-Scale Compute PlatformSYSTEM IPFEATU。

4、1 2025 THALES.All rights reserved.CVA6:SovereignOpen Source HW Bernhard QUENDTChief Technical Officer-Thales 2 2025 THALES.All rights reserved.83,000employees2024 key figures68A global footprintcount。

5、VeriCHERI:Exhaustive Security Verification of CHERI ProcessorsRISC-V Summit Europe12.15.05.2025,ParisAnna Lena Duque Antn,Johannes Mller,Philipp Schmitz,Tobias Jauch,Alex Wezel,Lucas Deutschmann,Moha。

6、Going BIG With the RISC-V EcosystemRISC-V Summit Europe 2025Larry Wikelius2Confidential Qualcomm Technologies,Inc.and/or its affiliated companies May Contain Trade SecretsAgenda2Specification and ISA。

7、RISC-V based GPGPU on FPGA:A Competitive Approach for Scientific Computing?Eric GuthmullerJrme FereyreRISC-V Summit Europe,2025-05-13 Scientific computing applications require 64b floating point comp。

8、Enhancing your RISC-V SoC debug&optimization with embedded functional monitors Unrestricted|Siemens 2025|Siemens Digital Industries SoftwareMat ODonnell,Software Architect LeadTessent Embedded An。

9、pulp-platform.orgpulp_ PlatformOpen Source Hardware,the way it should be!company/pulp-platformIntegrated Systems Laboratory(ETH Zrich)MemPoolFlavors:Between Versatility andSpecialization in a RISC-V 。

10、The RISE Project:Advancing RISC-V SoftwareLudovic Henry,RISE TSCNathan Egge,RISE TSCMay 2025Mobilizing Software Ecosystem for GrowthCollaboration&Community EngagementContinuous Software Porting a。

11、ChallengeAccepted:Python Packaging Infrastructure for the RISCV64 EcosystemEU Summit 2025,Paris 1Challenge Accepted:Python Packaging Infrastructure for the RISCV64 Ecosystem-RISC-V EU Summit 2025,Par。

12、1RISCV Big EndianCOPYRIGHT CODETHINK|LICENSED UNDER CCBY SA 4.0RISCV EU Summit 2025CODETHINK201IntroductionCOPYRIGHT CODETHINK|LICENSED UNDER CCBY SA 4.0Endianness What is Endianness?The order values。

13、Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREEAdeel Ahmad,Ahmad Tameem,Nouman Amir,Bilal Zafar,Saad Bin Nasir10 xEngineersOutlineGenerative AI workloadsIREE compilation w。

14、A RISC-V BASED ACCELERATOR FOR POST QUANTUM CRYPTOGRAPHYAmbily Suresh,Manuel Freiberger,Andrew Wilson,Diego Gigena-Ivanovich,Willibald Krenn010203040506OVERVIEWRISC-V Research at SALThe ISOLDE Projec。

15、COPYRIGHT(C)2025,ECLIPSE FOUNDATION.|THIS WORK IS LICENSED UNDER A CREATIVE COMMONS ATTRIBUTION 4.0 INTERNATIONAL LICENSE(CC BY 4.0)Contribution towards European sovereignty for embedded processors T。

16、Cloud-based RISC-V serversFabien Piuzzi,R&D Engineer,Scaleway LabsMay 14th 2025How and why we built them How you can use them3Who is ScalewayEuropean Leader in Public Cloud&AIFull service Clo。

17、Unleashing the Power of RISC-V E-Tracewith a Highly Efficient Software Decoder13 May 2025Unrestricted|Siemens 2025|Siemens Digital Industries Software|Marcel Zak,Mat ODonnell,Vivek Chickermane|RISC-V。

18、Pei-Hsiang Hung,Chung-Hua Yen,I-Wei Wu.Andes TechnologyAccelerating AI Models with Andes Matrix Multiplication (AMM)from CNN to LLM1TakingMainstreamSubject to change without notice copyright 2025 And。

19、From ISA to Industry:Accelerating Technical Progress and RISC-V adoption in 2025Andrea Gallo13th May 2025“RISC-V Poised for a Big 2025”Source:Embedded Processor ArchitecturesVDC Research,April 2025“R。

20、1The Significance of the RVA23 Profile in Advancing the RISC-V EcosystemMark Hayter,CSO and Co-Founder,Rivos Inc.Open ISASoftware Ecosystem(OSes,Platforms,Libraries,Domain specific applications)ISA:I。

21、Efficient Debug and Trace of RISC-V Systems:a hardware/software co-design approach Unrestricted|Siemens 2025|Siemens Digital Industries SoftwareOana Lazar,Embedded Software Engineer,Tessent Embedded 。

22、RISC-V on-chip debug&trace solution:Tessent UltraSight-VUnrestricted|Siemens 2025|Siemens Digital Industries SoftwareDevan Sharma,Account Technology Manager,Tessent Embedded Analytics Modern day 。

23、openEuler for RISC V Servers:Challenges&RoadmapYanjun Wu Deputy Director and Chief EngineerInstitute of Software,Chinese Academy of Sciences（ISCAS）May 2025 2 Content 1Brief Introduction of openEu。

24、RISC-V Europe Summit 2025LaunchpadWhats new at Codasip?Peter ShieldsRISC-V Europe Summit,Paris,May 20252 2025 Codasip.All rights reserved.Who is Codasip?Prague,CZBrno,CZAthens,GRHeraklion,GRThessalon。

26、100.000+installed debuggers10.000+customers40+%market share10.000+supported chipsEnabling Embedded Innovationswithxxxx Lauterbach,May 2025LEnablingThroughoutthe Whole SoC Life Cycle2Standar-dizationS。

27、Revolutionizing RISC-V Chip Design with AI AgentsDavid WangFounding ML Engineer,ChipAgentsBook a demo at chipagents.ai/#book-a-demoInput natural language specifications,documents,and instructions.Aut。

28、Towards Open-Source and Automatic PerformanceCharacterization HardwareMatthew Edwin Weingarten1Hardware architectSoftware developerWhy do we need performance characterization?Runs on2Why is my softwa。

29、XiangShan KMH:An Open Source RISC-V Core with 15/GHz for SPECCPU2006Yungang BaoMay 14th,20252 2OutlinePart I:The XiangShan ProjectPart II:Agile Chip Verification3 3RISC-V Brings New OpportunitiesSour。

30、Disposition:TitreSovereignty-Independence Innovation7 years of HW/SW codesign with RISC-V at CEAThomas Dombek thomas.dombekcea.frHead of CEAs LIST/DSCINDigital Systems and Integrated Circuits divisio。

31、Real Systems.Real Traction.Bringing High-Performance RISC-V Platforms to LifeBalaji Baktha,CEO,Ventana Micro SystemsRISC-V Europe Summit,Paris 2025Delivers a Full-Scale Compute PlatformSYSTEM IPFEATU。

32、RISC-V:POWERING THE FUTURE OF HIGH PERFORMANCE COMPUTING?Nick Brown(EPCC)n.brownepcc.ed.ac.ukWhy for HPC?1.Openness where anyone can freely take the standard and build compatible,but specialised,solu。

33、Ahead of Time Generation Ahead of Time Generation for GPSAGPSA Protectionin RISCRISC-V V Embedded CoresEmbedded CoresLouis Savary,Simon Rokicki and Steven Derrien/20Context2Embedded Systems Energy co。

34、RISC-V Heterogeneous Programming ParadigmAlibaba Damo Academy,XUANTIE TeamAtomic IO Enqueue(AIOE)Extension&AIOE with VirtualizationGUO RENCONTENTSMotivationHeterogeneous Computing Trends&Prob。

35、Scaling Open Compute:RISC-V,Chiplets,and the Future of AI and RoboticsWei-Han Lien Chief Architect 4Golden Age of Silicon DiversitySiliconSilicon HeterogeneityHeterogeneityArchitecture Architecture V。

36、Enter the RISC-VAI era with AndesNiraj DengaleAndes TechnologyTaking Mainstream2ConfidentialSubject to change without notice copyright 2025 Andes Technologymore featuresIntegrated Matrix Ext.(IME)8-c。

37、RISC-V ISA Extensions with Hardware Acceleration for Hyperdimensional ComputingRocco Martino,PhD Candidaterocco.martinouniroma1.itRISC-V Summit Europe 2025.Paris,12-15 May.Outline2RISC-V Summit Europ。

38、14|05|2025Edward WilfordSenior Research Director,AutomotiveA Safe Software Convergence:How Automotive and Industrial Designs are Eliminating Boundaries and Creating Opportunities Copyright 2025.All r。

39、1ESA UNCLASSIFIED-For ESA Official Use Only1RISC-V Summit Europe 2025,ParisRISC-V:Reaching New Orbits in Space ComputingLucana Santos(lucana.santosesa.int);Roland Weigand(roland.weigandesa.int)22RISC。

40、Improvements to RISC-V Vector code generation in LLVMLuke Lau,Alex BradburyRISC-V Summit Europe 2025RVV codegen developmentImprovements to RISC-V Vector Codegen in LLVMAlex Bradbury,Luke Lau,RISC-V S。

41、Enabling the Next Phase of RISC-V:Product Innovation and Scalable SE-solution to winI.RISC-V:Challenges&OpportunitiesII.ESWIN Computings Product InnovationIII.Enabling the Next Phase of RISC-VE-s。

42、RISC-V SUMMIT 2025RISC-V open designs and contributions to hardware security research and development activitiesAgence Nationale de la Scurit des Systmes dInformation(ANSSI)11 MARS 20251212/05/2025Te。

43、1AKEANA PROPRIETARY AND CONFIDENTIALBreaking Breaking Performance Performance BarriersBarriersRISC-V Summit 2025.Paris,FranceGraham Wilson Product Group2Processor IP company(RISC-V)Proven Performance。

44、1AKEANA PROPRIETARY AND CONFIDENTIALRISC-V Summit 2025:Paris,France2 minute Lightening2Processor IP company(RISC-V)Proven Performance LegacyTeam comprised of veterans from ThunderX2 ARM server chip d。

45、Utilizing RISC-V Trace Standards forEfficient Bugfixing and ProfilingNicolas Delemarre|Lauterbach GmbH|13.05.2025 LDriven by market requirements,embedded systems and chip architectures are becoming m。

46、Emanuele Venieri1,Simone Manoni1,Giacomo Madella1,Federico Ficarelli2,Daniele Gregori3,Daniele Cesarini2,Luca Benini1,4,Andrea Bartolini1emanuele.venieri2unibo.it1University of Bologna,Italy,2CINECA,。

47、From Open Silicon to Sovereign Supercomputing:EuroHPCs Vision for RISC-VRISC-V Summit Europe 14th May 2025|Alexandra Kourfali|Paris,FR EU body&legal and funding entity Created in 2018 Autonomous 。

48、RISC-V Powering Bespoke Silicon and European SemiconductorPablo ValerioEditor-Supply ChainBespoke Chips:Navigating Disruption and Supply Chain Challenges in the era of AI and HPCThe semiconductor ind。

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RISC-V欧洲峰会2025（RISC-V Summit Europe 2025）嘉宾演讲PPT合集（共60套打包）

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