RISC-V 高级中断架构的实时扩展.pdf

1、RISC-V Real-Time Interrupt ArchitectureRISC-V Summit Europe 2025Alexey Khomich,Evgenii Paltsev and Paul Stravers12-15 May 2025 2025 Synopsys,Inc.2RISC-V Real-Time Interrupt Architecture Motivation Trap Stack Pointer Management Nested Vectored Interrupts Real-Time Interrupt Delivery Bus-less Single C

2、ore Configuration Latency and Area Impact RTIA Development Status 2025 Synopsys,Inc.3 2025 Synopsys,Inc.3RISC-V Real-Time Interrupt ArchitectureMotivationMost features are covered by RISC-V Advanced Interrupt Architecture(AIA)which can be extended with:Nested vectored interrupts Low latency interrup

3、t delivery Light weight real-time interrupt architectureRequirementRISC-V AIAReal-Time(deterministic low latency)interruptsNoMulti-core configurations support YesVirtualization support YesInter-processor interrupts YesRISC-V ISA compliance,incl.H-extension YesUnified programming model YesFlexible in

4、terrupt routing YesBus-less single coreNo 2025 Synopsys,Inc.4 2025 Synopsys,Inc.4RISC-V Real-Time Interrupt ArchitectureTrap Stack Pointer Management Avoid stack-less execution in trap handler Reduce context store/restore overhead Allow hardware to automate trap frame Run-time configurable for each

5、privilege mode Compatible with all interrupt handling modes(Direct,Vectored)2025 Synopsys,Inc.5 2025 Synopsys,Inc.5RISC-V Real-Time Interrupt ArchitectureNested Vectored Interrupts New Nested Vectored interrupt handling mode Major interrupt reporting via IMSIC file(use iprio as EIID)External interru

6、pt vectors table:Shared exception trap vector Up to 255 high priority nested interrupts Lower priority chained interrupt(share single vector)Automatic external interrupt claim and jump by vector Interrupt complete triggered from software Interrupt threshold update at interrupt cl