RISC-V 片上调试和跟踪解决方案：Tessent UltraSight-V.pdf

1、RISC-V on-chip debug&trace solution:Tessent UltraSight-VUnrestricted|Siemens 2025|Siemens Digital Industries SoftwareDevan Sharma,Account Technology Manager,Tessent Embedded Analytics Modern day SoCs are complexUnrestricted|Siemens 2025|Siemens Digital Industries Software Complex SoC designMulticore

2、 Processor architecture Integration of complex IPs Complex Software Difficult to predict real-time behaviourCPU-CPU interactions Software optimization Huge amount of raw-trace dataRestricted|Siemens 2022|Sales|DISW/TessentTraditional SoC debug needs helpThe time and costs taken to debug and optimize

3、 software executing on complex RISC-V based SoCs are escalating Software code complexity Designs have multicore and multichips packaging techniques Heisenbugs and long-tail problems are difficult to identify&reproduce Silent data corruptionUnrestricted|Siemens 2025|Siemens Digital Industries Softwar

4、eLowdebugproductivityIdentifying hardware and real-time software issues require more efficient methods to debug,iterate,and scaleTessent UltraSight-VUnrestricted|Siemens 2025|Siemens Digital Industries SoftwareA comprehensive end to end debug&trace solution for RISC-V based SoCs Tessent UltraSight-V

5、Unrestricted|Siemens 2025|Siemens Digital Industries SoftwareRun control debug using GDB and OpenOCDwith code instrumentation for logging capabilitiesHighly-compressed processor trace(RISC-V E-trace spec)Fast system memory access for ELF file uploadsHW verified by RISC-V core vendors,silicon proven

6、down to 3nm and over 3GHzCompatible with 3rd party tools including VS Code and Lauterbach TRACE32Scalable to a complete SoC system-level debug,optimization,and monitoring solutionReduce costs,time taken to debug and optimize software executing on RISC-V SoCsTessent UltraSight-VUnrestricted|Siemens 2