超大规模集成掩模拼接区域快速布线算法.pdf

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1、Fast Routing Algorithm for Mask Stitching Regionof Ultra Large Wafer Scale IntegrationZhen Zhuang1,Quan Chen2,Hao Yu2,and Tsung-Yi Ho11The Chinese University of Hong Kong2Southern University of Science and TechnologyOutline Introduction Problem Formulation Technical Details Experimental Results Conc

2、lusion2Introduction Ultra large wafer scale integration is promising for ultra-high performance computing applications,such as AI and super-computing.The area of interposer is increasing:The interposer area of the TSMC CoWoS with 3.3X-reticle size is about 2700 mm21.In the future,the area of interpo

3、sers can be up to 5000 mm22.31 https:/ Hou et al.,“Supercarrier Redistribution Layers to Realize Ultra Large 2.5D Wafer Scale Packaging by CoWoS,”in ECTC,2023.Introduction Mask stitching technique is necessary for ultra large silicon interposer manufacturing.4IntroductionChallenges Effectiveness:sol

4、ve special design rules.Efficiency:tackle more than 10 thousands of signal nets.5Problem Formulation Input:Access point set,net set,RDL set.Output:Connect two access points of each net by vias,wires,and a stitching wire.Objective:Maximize routability and minimize wirelength.Design rule constraints:V

5、ia location:access point location.Stitching wire location:stitching region.Required routing pattern.Routing angle:0,90,or 135.Minimum spacing.6Technical DetailsRouting region tuning prepare the tuned region for special routing patterns.Routing algorithm w.conflict elimination Routing region initiali

6、zation:access point sorting.Conflict elimination:layer-by-layer procedure.Fast legal routing:candidate selection.7Technical DetailsRouting region tuning prepare the tuned region for special routing patterns.8Technical DetailsRouting algorithm w.conflict elimination Fast legal rou