FeFET 中异常电荷捕获的设备感知测试.pdf

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1、Device-Aware Test for Anomalous Charge Trapping in FeFETsSicong Yuan1Changhao Wang2Moritz Fieback1Hanzhi Xun1Mottaqiallah Taouil1Lin Wang3Nicol Bellarmino2Riccardo Cantoro2Said Hamdioui11232025 Asia and South Pacific Design Automation ConferenceMotivation FeFET emerges aspromising Non-Volatile Memor

2、y deviceTest solutions required for manufacturingTesting FeFET is still in its early stagesConventional defects:transistor defects,interconnect&contact defects=Traditional approach Challenge in testingFeFET specific working mechanism=Unique defects in FeFETsTraditional approach detecting unique defe

3、cts result in high escapesSolutionDevice-aware Test specialized for unique defectsContributionsCharacterization of a new unique defect Anomalous Charge Trapping(ACT)Defect modelling&fault modelling Dedicated test solutions for ACTC.Wang et.al.,ITC,2024Dnkel,Stefan et.al.,IEDM,2017L.Wu et.al.,ITC,201

4、8D.Thapar et.al.,ITC,2023March 7,20252Outline FeFET Basics Defect mechanism&characterization Device-aware test methodology Defect modeling Fault modeling Test solutions ConclusionMarch 7,20253FeFET basicsMarch 7,20254FeFET structure:Ferro-electrical layer(FE layer)MOSFET-like structure FeFET state:H

5、igh threshold voltage(HVT)0 state,high resistance Low threshold voltage(LVT)1 state,low resistance 1 FeFET-1 R cell:Write operation Read operation 3x3 FeFET array NOR-Flash structureFE layerHVTLVT(a)(b)(c)(d)(e)Defect mechanism&characterizationMarch 7,20255Measurement method:Id-Vgmeasurement Repeati

6、ng 1 write-1 read Write voltage sweeping in write operationsLow memory window(MW):In HVT state,Vthlower trending In LVT state,Vthhigher trending MW reduceId-Vgcurve no shifting:Defective Id-Vgin the middle of defect-free Id-Vg-4-202410-510-410-310-210-1100Measurement at Vd=100 mV Defective,MW 1.6 V