eetop.cn_T2 - Fundamentals of DRAM I O Standards and Circuits.pdf

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1、 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025 TutorialsFundamentals of DRAM I/O:Standards&CircuitsHye-Ran KimFeb.16,2025T2:Fundamentals of DRAM I/O:Standards and CircuitsHye-Ran Helen Kim1 of 72 2025 IEEE International Solid-State Circuits ConferenceOutline DRAM I/O and Applicat

2、ions DRAM Application Signaling and Clocking I/O Speed Extension Equalization Training and Calibration Link Protection Present and Future DRAM ConclusionT2:Fundamentals of DRAM I/O:Standards and CircuitsHye-Ran Helen Kim2 of 72 2025 IEEE International Solid-State Circuits ConferenceSelf Introduction

3、 PhD degree from Sungkyunkwan University,Korea in 2020 Have been with Samsung Electronics since 2006 and Principal Engineer(2019 Now)Developed various commodity DRAMsGDDR5/6/7 and LPDDR4/5 Memory Standardization in JEDECGDDR7 and LPDDR5 Member of ISSCC Technical Program Committee(2021 Now)Research i

4、nterests:I/O interfaces and Memory ArchitectureT2:Fundamentals of DRAM I/O:Standards and CircuitsHye-Ran Helen Kim3 of 72 2025 IEEE International Solid-State Circuits ConferenceDRAM Trend in ISSCC2025Many core computing enabled the dramatic enhancement in GPU performance.However,the pace of DRAM BW

5、improvement is catching up only half of that.Not only bandwidth but also power efficiency improvement is important to satisfy the thermal constraint of the system.T2:Fundamentals of DRAM I/O:Standards and CircuitsHye-Ran Helen Kim*https:/ of 72 2025 IEEE International Solid-State Circuits Conference

6、Whats Memory I/O?Definition:Input/Output Pins and Relevant Circuitry(=I/O Interface)Purpose:To communicate with SoC(CPU,GPU,)5 of 72CADRAMDQI/O InterfaceLogic&CoreDRAMDRAMCPUI/O InterfaceLogic&CoreCKWCKRDQSInputInputInputoutputoutputI/O=Input/OutputInput Pin Description CK:Clock for command&address