Session 23AI-Accelerators.pdf

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1、Session 23 Overview:AI-Accelerators DIGITAL ARCHITECTURES AND SYSTEMS SUBCOMMITTEEAI hardware accelerators are driving innovations in modern computing,influencing generative AI,large language models,and 3D point cloud analysis.The initial papers focus on reducing external memory accesses and enhanci

2、ng energy efficiency through hardware-aware algorithms and novel processing units.Later papers highlight the need for energy-efficient solutions for edge devices and scalable AI systems,showcasing advancements in optimizing AI hardware for cloud and edge applications.These innovations reflect ongoin

3、g efforts to enhance performance and efficiency in AI hardware design.Session Chair:Soojung Ryu Seoul National University,Seoul,Korea Session Co-Chair:Hugh Mair MediaTek,Dallas,TX 404 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 23/AI-ACCELERATORS/OVERVIEW979-8-3315-4101

4、-9/25/$31.00 2025 IEEE8:00 AM 23.1 T-REX:A 68-t o-567s/Token 0.41-t o-3.95J/Token Transformer Accelerat or wit h Reduced Ext ernal Memory Access and Enhanced Hardware Ut ilizat ion in 16nm FinFET Seunghyun Moon,Columbia University,New York,NY In Paper 23.1,Columbia University and Intel present a 16n

5、m FinFET,10.15mm2 transformer accelerator that reduces external memory accesses(EMA)and enhances hardware utilization.Algorithmic model compression lowers EMA by up to 31,while the chip achieves processing times of 68-567s/token and energy consumption of 0.41-3.95J/token.8:25 AM 23.2 A 28nm 0.22J/To

6、ken Memory-Comput e-Int ensit y-Aware CNN-Transformer Accelerat or wit h Hybrid-At t ent ion-Based Layer-Fusion and Cascaded Pruning for Semant ic-Segment at ion Pingcheng Dong,The Hong Kong University of Science and Technology,Hong Kong,China AI Chip Center for Emerging Smart System,Hong Kong,China