HC2022.UTokyo.Kota_Shiba.v01.pdf

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1、Kota Shiba,The University of Tokyo A 7-nm FinFET 1.2-TB/s/mm23D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers2022 Hot Chips 34 SymposiumAug.21 23,Virtual ConferenceKota Shiba1,Mitsuji Okada2,Atsutake Kosuge2,Mototsugu Hamada2,

2、and Tadahiro Kuroda21The University of Tokyo,2Research Association for Advanced Systems(RaaS)2/14Kota Shiba,The University of Tokyo A 0.7-pJ/bit,8.5-Gbps/link inductive coupling inter-chip wirelesscommunicationinterfacefora3D-stackedSRAMhasbeendeveloped in a 7-nm FinFET process.A new physical placem

3、entmethod that allows coils to be placed over off-the-shelf SRAMmacros with small magnetic field attenuation,together with theuse of synchronous communication using Manchester encodingand a clocked comparator to enable the detection of small-swingsignals,achieve a 26%reduction in SRAM die area compa

4、red toTSV-based stacking.Inter-chip communication at 0.7-pJ/bit,8.5-Gbps/link was confirmed using test chips.A 4-hi 3D-stacked SRAMmodule using the proposed interface is estimated to achieve a 1.2-TB/s/mm2area efficiency,representing a two-orders-of-magnitudeimprovement over state-of-the-art 3D-stac

5、ked SRAM.Abstract3/14Kota Shiba,The University of Tokyo Mobile AI devices need high-bandwidth,low-latency memory with small form factor 3D-stacked SRAM(3D-SRAM)can meet these demands But current 3D-SRAM using TSV and m m-bump has issues with cost,yield and area efficiency 12IntroductionSRAMLogic3D-s

6、tacked SRAM with TSV and m m-bump 121 K.Cho,et al.,Hot Chips,2020 2 S.-K.Seo,et al.,ECTC,2021SiTSVCostYieldSim m-bump40 m mm4/14Kota Shiba,The University of Tokyo To eliminate TSV and m m-bump,ThruChip Interface(TCI)is proposed,which is a wireless version of TSV TCI is compatible with standard CMOS