04-陈拓.pdf

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1、Tuo Chen(陳 拓)()Suzaki Lab(須崎研究室)Institute of Information Security(IISEC),Japan2024-08-23A Study on Transient Execution Vulnerabilities of RISC-V Implementations(RISC-V 实现的瞬态执行漏洞研究)RISC-V Summit China 2024(RISC-V 中国峰会 2024)Thiis work is licensed under CC BY-SA 4.0 2 2Self introductionAbout meMaster s

2、tudent Tuo Chen(陳 拓)IISEC(2023):information security of open hardwareRenesas Electronics group(20172023):prototype evaluation,device test,mass production setup for semiconductor tests,export procedures,etc.NUAA,CEIE(20132017):electronic circuit,microwave systems and devicesAbout IISEC Suzaki Lab:htt

3、pps:/lab.iisec.ac.jp/suzaki_lab/index-e.htmlProf.Kuniyasu Suzaki（須崎有康教授）Research topics:RISC-V,TEE,virtualization,confiddential computing,etc.Currently other members are researching on:FPGA cryptography applications,malicious activity statistics,fuzzing for security purposes,vehicle cyber security,i

4、nfosec of IoT devices,confiddential computing+TEE3 3BackgroundCache timing side-channel attpack(SCA)TechniquesTransient execution vulnerabilitiesSummary of review papersSpectre attpacksFeasibility on RISC-V implementationsMitigationConclusionContents4 4Background(1)Out-of-order(OoO)executionParadigm

5、 that allows subsequent instructions in the pipeline to be executed ahead of or concurrently with preceding ones,rather than strictly adhering to program order(=in-order execution).A OoO CPU temporarily stores executed instructions in the reorder buffeer,and later adjusts the order in which they are

6、 refleected in the registers during the retire stage,thereby achieving the same results as an in-order processor.Mainstream x86 CPUs and some ARM processors have adopted OoO execution.Commercial RISC-V OoO core designs are still relatively few,but their numbers are growing rapidly.Source:httpps:/ Ca