005-haoluan.pdf

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1、August 2024Hao LuanChief ArchitectRISC-V Summit China 2024https:/ Interconnect Architectures for High-performance and Complex RISC-V SoCs基于 RISC-V 复杂高性能 SoC 的互联架构优化1Confidential 2024 Arteris,Inc.The Opportunities and ChallengesInterconnect is the Enabler for High Performance&Complex SoCs Confidentia

2、l 2024 Arteris,Inc.2John L.Hennessy and David A.Patterson.2019.A new golden age for computer architecture.Commun.ACM 62,2(February 2019),4860.https:/doi.org/10.1145/3282307A.Gholami,Z.Yao,S.Kim,C.Hooper,M.W.Mahoney and K.Keutzer,AI and Memory Wall,in IEEE Micro,vol.44,no.3,pp.33-39,May-June 2024,doi

3、:10.1109/MM.2024.3373763 Dr.John L.Hennessy and David A.Patterson predicted a few years ago that we are right in a new golden age for computer architecture with a few trends below:Open Instruction Sets Domain Specific Architecture Agile Chip DevelopmentHowever,the peak compute of server-grade AI har

4、dware has increased over 60,000 x over the past 20 years,as opposed to 100 x for DRAM or 30 x for the interconnect bandwidthChallenges of RISC-V SoCs Interconnect is the Problem to Address3Diverse interface protocols(ACE,CHI,ACE-Lite,AXI.)Varying coherency models(MESI,MOESI)Memory wall-Massive memor

5、y bandwidth of AI/MLSafety standards for automotive functional safety Verification/Performance models/FPGAsPhysical implementation(PD)Confidential 2024 Arteris,Inc.System IP and Network-on-Chip(NoC)SoC Interconnect IPsNetworking techniques for improved on-chip communication&data flowConfidential 202

6、4 Arteris,Inc.4Arteris Ncore cache coherent interconnect IPArteris FlexNoC non-coherent interconnect IPArteris CodaCache last-level cacheArteris Ncore Arteris FlexNoCChiplet LinkCHI&ACE ProtocolsProxy$SMC$Memory SubsystemHigh Speed Wired PeripheralsWireless SubsystemSecurity Subsystem I/O Peripheral