25-臧博.pdf

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1、Accelerate RISC-V SOC SW/HW co-development with mixed Emulation platformsZang Bo Intel Pre-Si “Shift Left!”Big Challenges:RISC-V SOC becomes bigger and more complex.Hard to figure out all HW RTL bugs with only UVM verification.Huge software enabling efforts for RISC-V SOC power on stage.Pre-Si Platf

2、ormsEmulator HW(RTL)Simulator-SWHybrid Sim/EmuHybrid modeling type(simulator+emulator)RISC-V CoreFPGA/ZebuSimulatorEmulatorRISC-V SW/HW co-develop based on mixed emulation platformsFull RISC-V SoC on ZebuAXIRISC-V coreNoCPCIe subsystemPCIe subsystem E-2-E on FPGAPCIe standalone IP on UVMPCIe Control

3、ler IPAXI AgentPCIe Endpoint AgentAXIPIPEUVMZebuFPGAAXIAXIPCIe PHY cardPIPEReal PCIe deviceHWSWPCIe controller register program reference scripts:PCIe link up PCIe speed change PCIe low power control Cfg/Mem accessPCIe controller driver.PCIe device driver:NVMe driver(PCIe SSD).Network stack(PCIe ethernet card)Graphics driver(PCIe graphics card)Complex scenarios:PCIe p-2-p transfer PCIe to DDR DMA Full SOC boot flowMixed Pre-Si platforms in product life cyclesThanks!