21-范宇杰.pdf

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1、5 Levels of RISC-V Processor Verification20 August 2024Yujie Fan,Aimee Sutton,Larry Lapides 2024 Synopsys,Inc.25 Levels of RISC-V Processor Verification The RISC-V Verification Disconnect 5 levels of processor verification Asynchronous lockstep continuous compare SummarySynopsys Confidential Informa

2、tion 2024 Synopsys,Inc.3The RISC-V Verification DisconnectRISC-V Core User:Expects core quality to be the same as ARM 1015 verification cycles=104 RTL simulators running 24/7!RISC-V Core Developer:Needs to deliver high-quality corePotential issues with necessary expertise,methodologies,technologies,

3、resources 2024 Synopsys,Inc.4Challenges in RISC-V Processor Verification Design complexity architecture,micro-architecture,implementation choices,custom features Source of processor IP(in-house,open source,vendor+custom instructions)Use case:microcontroller application processor;closed versus open t

4、o external software development Verification productivity and time to closure Team experience(designers and verification engineers)Processor verification methodology Tool selection 2024 Synopsys,Inc.55 Levels of RISC-V Processor DV Methodology 1)Asynchronous lockstep continuous compare2)Synchronous

5、step-and-compare3)Post-simulation trace log file compare4)Self-checking tests 5)“Hello World”,Linux boot,CPUQuality 2024 Synopsys,Inc.65 Levels of RISC-V Processor DV Methodology 1)Asynchronous lockstep continuous compare2)Synchronous step-and-compare3)Post-simulation trace log file compare4)Self-ch

6、ecking tests 5)“Hello World”,Linux boot,CPUQuality 2024 Synopsys,Inc.7Post-sim Trace Compare(entry level DV):Pros and Cons Pros:Simple to set up and use Cons:Must run RTL simulation to the end Cannot debug live Incompatible trace formats(between RTL,ISS,)Easy to skip instructions,and only compare se