025--HaichengLi-XiaoWang.pdf

1、Soft-ISA:kernel built-in emulation engine to extend RISC-V silicon ISA capabilityHaicheng Li Xiao Wang Intel ConfidentialDepartment or Event Name2RISC-V Summit China 20242Legal Notices and DisclaimersStatements in this document that refer to future plans or expectations are forward-looking statement

2、s.These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements.For more information on the factors that could cause actual results to differ materially,see our most

3、recent earnings release and SEC filings at .All product plans and roadmaps are subject to change without notice.Any forecasts of goods and services needed for Intels operations are provided for discussion purposes only.Intel will have no liability to make any purchase in connection with forecasts pu

4、blished in this document.Code names are often used by Intel to identify products,technologies,or services that are in development and usage may change over time.No license(express or implied,by estoppel or otherwise)to any intellectual property rights is granted by this document.Intel Corporation.In

5、tel,the Intel logo,and other Intel marks are trademarks of Intel Corporation or its subsidiaries.Other names and brands may be claimed as the property of others.This document contains information on products and/or processes in development.Intel ConfidentialDepartment or Event Name3RISC-V Summit Chi

6、na 20243Challenge of Compatibility RISCV Advantages Highly customizable ISA Die size-PnP efficiency Fast evolving ISA extensions RISCV Pain Points HW profiles vs.Chip diversity Software compatibility HW readiness vs Fast evolving ISARISC-V SoC(w/o RVV)Android AOSP3rd Party APP(w/RVVV 1.0)illegal and