SESSION 29 SRAM.pdf

1、ISSCC 2025SESSION 29SRAM29.1:A 38.1Mb/mm2SRAM in 2nm CMOS Nanosheet Technology for High density and Energy Efficient Compute Applications 2025 IEEE International Solid-State Circuits Conference1 of 34A 38.1Mb/mm2SRAM in 2nm CMOS Nanosheet Technology for High Density and Energy Efficient Compute Appl

2、icationsTsung-Yung Jonathan Chang,Yen-Huei Chen,K.Venkateswara Reddy,Nikhil Puri,Teja Masina,Kuo-Cheng Lin,Po-Sheng Wang,Yangsyu Lin,Chih-Yu Lin,Yi-Hsin Nien,Hidehiro Fujiwara,Ku-Feng Lin,Ming-Hung Chang,Ching Wei Wu,Robin Lee,Yih Wang,Hung-Jen Liao,Quincy Li,Ping Wei Wang,Geoffrey Yeap.29.1:A 38.1M

3、b/mm2SRAM in 2nm CMOS Nanosheet Technology for High density and Energy Efficient Compute Applications 2025 IEEE International Solid-State Circuits Conference2 of 34Semiconductors Empower Innovations,Enrich Lives229.1:A 38.1Mb/mm2SRAM in 2nm CMOS Nanosheet Technology for High density and Energy Effic

4、ient Compute Applications 2025 IEEE International Solid-State Circuits Conference3 of 34Semiconductors Empower Innovations,Enrich Lives320102012201420162018Logic Density 202020222024N3PN2N16N10N7N6N5N4N3EN20N28NanosheetLow-R MEOL/BEOLSelf-Aligned FeaturesLow K SpacerFinFlex with 1-FinFinFETEnhanced

5、Strained-SiHigh Density MIMHigh-KMetal GatePlanarLow R MEOLHigh Mobility Channel Super High Density MIMDouble PatterningEUV2025K.Zhang,2024 ISSCC;Y.Chen,et al.,2014 ISSCC29.1:A 38.1Mb/mm2SRAM in 2nm CMOS Nanosheet Technology for High density and Energy Efficient Compute Applications 2025 IEEE Intern

6、ational Solid-State Circuits Conference4 of 34Outline 2nm technology highlight SRAM bit cell and scaling trend SRAM design techniquesMaximize bit cell array efficiencyFar-End(FE)-write assistFE-pre-chargerDouble pump SRAM design for HPC Silicon results Summary 29.1:A 38.1Mb/mm2SRAM in 2nm CMOS Nanos