SESSION 22 - High-Speed Analog-to-Digital Converters.pdf

1、ISSCC 2024SESSION 22High-Speed Analog-to-Digital Converters22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference1 of 52Yuefeng Cao1,Minglei Zhang1,Yan Zhu1,Rui P.Martins1,2and

2、Chi-Hang Chan11State Key Laboratory of Analog and Mixed-Signal VLSI,University of Macau,Macau,China2Instituto Superior Tecnico/Universidade de Lisboa,Portugal 22.1 A 12GS/s 12b 4 Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer22.1:A 12GS/s 12b 4

3、Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference2 of 52OutlineMotivationComprehensive Calibration of TI ErrorsConceptImplementationLinearized Input BufferHigh-Speed ChannelMeasurement Result

4、sConclusions22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference3 of 52MotivationEmerging Wireless Communication&Automotive RadarWide-Band Challenges on Direct RF-Sampling ADC

5、 10GS/s Sampling Rate(Necessitating Interleaving&High-Speed Channel)Simple and Condition-Robust Skew CalibrationHigh Linearity Over Wide BWLow Power Consumption and Compact AreaHigh LinearityIntegration Friendly 22.1:A 12GS/s 12b 4Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI E

6、rrors and Linearized Input Buffer 2024 IEEE International Solid-State Circuits Conference4 of 52Review of Prior ADC Design2.25GS/s per Channel:Low TI-Factor Pre-Channel Sampler:High BW,Less Critical Instants Ali,ISSCC2012b 18GS/s8x-Time Interleaved 1300mW in 16nm2-Rank Interleaving Architecture:2-TI