11.High Performance RISC-V Chiplets for Cloud and Edge Computing - final.pdf

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1、High Performance RISC-V Chiplets for Cloud and Edge ComputingJeff Maguire,Director of Product ManagementAugust 24,2023THE RISC-V PERFORMANCE LEADER2Chiplets Are Key To Extend Moores LawSource:Synopsys,https:/ may prove to be more economical to build large systems out of smaller functions,which are s

2、eparately packaged and interconnected1.”-Gordon E.Moore1:“Cramming more components onto integrated circuits”,Electronics,Volume 38,Number 8,April 19,1965Ventana with DSAChiplet Solutions3CPU cluster/chipletCPU cluster/chipletCPU cluster/chipletD2D linkDiscrete CPUDevice Attach:brings devices in-pack

3、age as chiplets,connected over D2D with device protocols(CXL)Die Disaggregation Unlocks Innovation CHI-based CoherentOn-chip InterconnectPCIe/CXLComputeDeviceTraditional PCIe/CXL Attached AcceleratorDomain SpecificAccelerator Programmable AcceleratorD2D PHYCHI-based CoherentOn-chip InterconnectPCIe/

4、CXLCPU Cluster Proxy(Controller)Accelerator VentanasChiplet ArchitectureProxies represent the chiplets,unpacking D2D transport streams into protocol transactions on the SoC block interfaceDie Disaggregation:breaks a monolithic SoC into chiplets,which can then be composed into systems using SoC proto

5、cols over D2D(CHI,AXI)Ventana chiplets are CPU cluster interfaced over a D2D link with AMBA CHI protocolIntegrated PackageAccelerators typically interface with AXI or ACE-LiteVentanas Chiplet Architecture enables Chiplet vs IP integration to be interchangable4Pioneering Efficient Chiplet Interconnec

6、t ControllerRequirements Low D2D latency Predictable memory performance Standard SoC buses and networks must map easily to D2D transport CHI,AXI,HW memory coherency for efficient support of acceleratorsUCIe or BoW D2D Physical LayerVentana ControllerUCIe or BoW D2D Physical LayerChiplet AChiplet B 7