通用芯片间接口标准——通往OCP芯片市场互操作性的道路.pdf

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1、Jeff Maguire,Ventana Micro SystemsDavid Kruckemyer,Ventana Micro SystemsUniversal Die-to-Die Chiplet Interfacing Standards The Road to Interoperability within the OCP Chiplet MarketplaceSERVER:OPEN CHIPLETECONOMYChiplet Die Disaggregation IP Protocols become chiplet interfaces Agnostic to chiplet ar

2、chitectureIndependent of TransportSPEC,Universal D2D Transaction and Link LayerApproved OCP Contribution this year to extend the PHY interfacing beyond BoW to UCIe!Independent of Link Management Leverage native PHY bring-up mechanismsChiplet SiP=Monolithic SoC Once chiplet links are brought-up,the c

3、hiplet integration behaves like a monolithic SoCUniversal Die-to-Die Chiplet InterfacingLeverage existing protocol interoperability between IP vendors(e.g.AMBA)Universal to bridge any protocol to any physical layer(now including UCIe)Low-latency to approximate the performance of monolithic SoCs Low-

4、overhead to scale from high-performance to cost-effective integrationsRobust FEC/ECC vs CRC/Retry to cover the most demanding applications(e.g.FuSa)Freedomto disaggregate to any desired chiplet architectureOpenecosystem to establish chiplet interoperability standardsOCP Open Chiplet Economy Project

5、is a unique vendor-neutral Community where all are allowed to contribute and define chiplet standardsChiplet Interfacing GoalsUniversal Transaction Layer Interface to any system protocol interface Packetize/Depacketize interface signals dynamically to TLPs Manages credit-based flow per TLP streamUni

6、versal Link Layer Packs/Unpacks TLPs into/from LLPs Protects TLPs with FEC/ECC Trains/Aligns fragments Simple binding to any desired Physical LayerPhysical Layer Interfacing BoWinterfacing to low-level PHY UCIe interfacing to upper-level PHY Adapter Layer(FDI)Universal Transaction and Link Layer(U-T