加速CXL实际部署：从硬件辅助智能分层到压缩内存原型.pdf

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1、Nilesh Shah,VP,ZeroPoint Technologies Jungmin Choi,Director,SK hynix AmericaAccelerating Real-World CXL Deployments:From Hardware-Assisted Intelligent Tiering to Compressed Memory PrototypesSERVER:COMPOSABLE MEMORY SYSTEMS(CMS)2:1 compression ratio is realistic in a variety of workloads.Data with 2:

2、1 compression halves the media cost.Compressed Memory:Cheaper Tier2025 Conference Concepts,Inc.All Rights ReservedFrom SW to HW based compressionData centers are spending capacity on software-based compression.4.6%*3%*CPU cycles used for compression:Meta&Google have stated that a hardware compressed

3、 memory tier is a must-have.*https:/dl.acm.org/doi/abs/10.1145/3579371.3589074*https:/ieeexplore.ieee.org/document/101581612025 Conference Concepts,Inc.All Rights ReservedNon linear DIMM cost($/GB)versus capacityHigher$/thread cost with increased thread countTCO advantage with Medium capacity(recycl

4、ed)DDR4 DIMMs over CXL vs higher capacity direct attached DDR5 DIMMs to enhance GB/ThreadFundamental ObservationsCost non linearity=CXL OpportunityInline Compression enabled CXL FPGA deviceSignificant TCO savings with minimal latency impact(cache line compression)Compression Ratio across Application

5、s(Renaissance,SPEC,Hyrise,HPCG)Cache Line Algorithm 1KB block:1.85x on averageDRAM DRAM+CXLDRAM+Compressed CXLCompression Ratio111.8TCO$44.5k$35.7k$33.6kSavings0%(baseline)20%4 CXL modules33%2 CXL Modules,with 2X compressionExample TCO ResultsLLM Models:1.5X compressed,KV Cache 2X compressed with ca

6、che line compression!Compressing AI modelsCacheCache-line compression is line compression is capable to compress capable to compress AI workloadsAI workloadsAverage Read Latency of DenseMem+Memory(no CXL ctrl)DenseMem decompression has minimal impact on latencyAverage latency is even improved in som