人工智能_高性能计算闪电演讲.pdf

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1、AI/HPC Lightning TalksWongyu Shin,Technical Leader of HardwareChip Design Strategy in AI Application EraGrowing Design ComplexityAdvanced Process Nodes:Increasing transistors(7nm 5nm 4nm 3nm)Beyond reticle:Multi-core Multi-chip module Multi-chiplet 3D LargePackage Size(120mm x 150mm)SLP(substrate-li

2、ke PCB)Beyond package:Scale-up(OAI UBB Backplane fabric within a Rack)Scale-out(Backplane fabric across Racks)Turnaround Time(TAT)PressureKey Challenges Today18 months per package(tape-out)2-3mm)Decoupling the Layers:Protocol vs.Adapter(Link)Strategic Directions for Logical&System-Level Interoperabi

3、lityAddressing Protocol Divergence with Semi-Standard&High-Utilization ProtocolsOptimizing Latency with 256B Latency-Optimized FlitOvercoming Bandwidth Discrepancy:Speed HarmonyBroader Interoperability:Protocols Across Different Physical LinksConclusion&The Collaborative Path ForwardBy clearing defi

4、ning the issues,we can strategically direct our efforts towards robust solutionsFostering broader interoperability by enabling protocols to span various physical links will unlock new levels of system design flexibility and scalabilityStrategic Imperatives&Community Co-working DirectionThank You!Shr

5、ikanth VenkateshappaHow Multi-Voltage Systems Reshape Cost,Efficiency&SustainabilityAI rack power is explodingTakeaway:The current low-voltage approach is inefficient,material-heavy,and unsustainable at AI-scale rack power.Modern AI compute racks will exceed 1 MW each,far above legacy design expecta

6、tions.At 48 V,delivering 1 MW requires 20,833 A,forcing 3 tonnes of copper per MW costly,heavy and difficult to install&operate151026601201401803606001000020040060080010002015201820202023202420252026202720282030Rack Power(kW)YearRack PowerRack PowerNvidia DGX-2(10 kW)Rubin(180 kW)Nvidia DGX B200 rac