5.结合Andes ACE框架与AndesCycle加速RISC-V自订指令开发.pdf

1、TakingMainstreamConfidentialSubject to change without notice copyright 2025 Andes Technology结结合合 Andes ACE 框架与框架与 AndesCycle 加速加速 RISC-V 自自订订指令开指令开发发顏敬哲顏敬哲,陳枝懋陳枝懋,吳吳奕緯奕緯晶心科技AndesTechnologyTakingMainstream2ConfidentialSubject to change without notice copyright 2025 Andes TechnologyOutlineACEFramework

2、OverviewAndesCycleSimulatorCaseStudies:VideoCodecExtensionSigmoidFunctionAccelerationTakingMainstream3ConfidentialSubject to change without notice copyright 2025 Andes TechnologyBuilding Custom RISC-V Extensions with ACEAndesCustomExtension(ACE)frameworkEnabledesignerstocreatecustomCPUinstructionson

3、AndesCoreprocessors.KeyfeaturesSupportbothcustomscalar(ACE-Scalar)andvector(ACE-RVV)instructionsProvideastraightforwarddesignflowDescribeinstructionbehaviorinanACEdefinitionfileImplementthehardwarelogicinaconciseVerilogfileCustom-OPtimizedInstructiondeveLOpmentTools(COPILOT)Generateextendedsourcecod

4、eforcompiler,debuggerandinstructionsetsimulator(ISS)ProduceVerilogcodeforACEengineRTLintegrationTakingMainstream4ConfidentialSubject to change without notice copyright 2025 Andes TechnologyConcise Verilog fileincludesCorelogicsNOTE:CanbecombinatorialorsequentialACE definition file includesInstructio

5、nname,operandsCmodelblockExecutionlatencyAn Example of Designing Custom Instructions(1/2)insn myadd op=out xrf dout,in xrf din,imm5 din2;csim=%dout=din+din2;/C Model%;latency=1;.ace/ACE_BEGIN:myaddassign dout=din+27d0,din2;/ACE_END.vCOPILOTTakingMainstream5ConfidentialSubject to change without notic

6、e copyright 2025 Andes Technology/ForBinutils2.35andlater.staticintmatch_ace_opcode_3(conststructriscv_opcode_3*op,insn_tinsn)return(insnop-match)&op-mask)=0;constace_keyword_tace_keywords=acrw200_0,0,0,acrw200_1,1,0,acrw200_2,2,0,acrw200_3,3,0,acrw200_6,6,0,acrw200_7,7,0,acrw200_8,8,0,acrw200_9,9,0