029-郑律.pdf

1、Lv ZETALOG ZhengRISC-V IO Virtualization Implementation on X100X100-RISC-V Virtualization InfrastructureRISC-V High Performance Core w/CPU VirtualizationHigh Performance RISC-V Core 64-bit high performance RISC-V processor RVA2023 compatible RV64GCVBH Spec2k6Int 9.0/GHz 2.5GHzT12 Full RVV1.0 support

2、 SpacemiT IME(Integrated Matrix Extensions),4-core fusion AI computing power INT8 2.5TOPS 2.5GHzT12 Multi-core,multi-cluster,maximum 64-cores per chip CHI bus interface,and multi-die,multi-chip support Server spec security,RAS,debug facilitiesFull RISC-V Hypervisor Extension Support Hypervisor exten

3、ded S(HS)modeHS-mode CSR,time delta HPMGuest page/virtual instruction fault/HS-mode ECALLVSEI/VSTI/VSSI Virtualization Mode(V)Virtualized supervisor(VS)mode/Virtualized user(VU)modeVS-mode background CSRECALL from VS-mode/VU-mode Address translationshgatp pointing to G-stage translation tablevsatp p

4、ointing to VS-stage translation tablePTW/TLB with GPA support InstructionsHS-mode system barrierGuest memory accessRISC-V IO Virtualization ArchitectureRISC-V IO VirtualizationIO Virtualization Solutions Community present conditionS2 direct DMA access in guest OSVFIO supports PCI and IOMMUIOMMU is a

5、 VFIO building block to create S2 remapping of VFIO device IO regions(VFIO_IOMMU_MAP/UNMAP_DMA)VFIO_PCI binds SR-IOV virtual function to guest OSMSI based IRQ virtualization/dev/kvm setup AIA attributesAssociate KVM eventfd/irqfd with AIA VS interrupt file using architecture specific hooks Community

6、 future trendsKVM IRQ BypassS1+S2 supportVirtIO Data Path Acceleration(vDPA)Guest OS owns PC,S1 tables,pointers in PC,S1 PPNs should exhibit implicit S2 translationsAIA Applications AIA v1.0 compliant Major IRQ priority Virtual interrupt,VTI GEILEN=8 WSI and MSI support 1023 APLIC interrupt sources