010-DmitryZakharov.pdf

1、RISC-V P Extension Implementation and DSP Application PracticeDmitry Zakharov08.2024CloudBEAR Introduction2 RISC-V IP company Est.2015 Gen.1 IP multiple time licensed Gen.1 IP based silicon in mass production Gen.2 cores are available for licensingRISC-V Processor IPBMBMseriesseriesBRBRseriesseriesB

2、IBIseriesseriesMicro-controllers3BR-652BR-352BR-651BR-351BR-350BR-650BI-350BI-652BI-651BI-671BM-310BM-610BI-672Gen.1Gen.2Bx-3xx:RV32 Bx-6xx:RV641-wideFast and compact coresApplication cores2-wide2-wide,OoO 2-wide 3-wide,OoOIntroductionWhat is a P extension?RISC-V Packed SIMD ExtensionInstruction set

3、 to accelerate integer and fixed pointmath using general purpose registers(GPR).330 instructions for SIMD,Partial-SIMD,Non-SIMDoperations.SupportsRV32 and RV64 architecture8,16,32,64 bit depth dataQ notation data(Q7,Q15,Q31)Merged math operations to combine multiply,accumulate,shift,round,saturate.P

4、 extension is useful to speed up DSP algorithms atedge devices with limited resourcesN bit valN bit valN bit value N bit valueN bit resN bit res16b16b16b16b32b32b32b AccumSAT.Q316 Basic operations in 1 instruction(RV32)5CLIP CMPMIN ABSOPOPOPSCalculation Up to 4 values in parallel(RV32)Programming Mo

5、delThe instructions operate on XLEN general purpose integer registers(GPRs).Registers are considered as small vectors divided into N values of a given bit depth.The specific interpretation of input and output registers is determined only by the instruction itself.An operation is performed on all val

6、ues in the vectors.The output vector format can be preserved(N-to-N)or changed(N-to-M or N-to-1).RV32 supports 64-bit data.Such operands are composed of an even-odd pair of 32 bit GPRs.Only the even register is used explicitly in the instruction.Overflow/saturation is reflected in the VXSAT control-