3189 - Simplifying Electronic Chip Design and Automation-10-20.pdf

1、October 21-24,2024Mandalay Bay Convention CenterLas Vegas,Nevada#3189Simplifying Electronic Chip Design Simplifying Electronic Chip Design and Automationand Automation using Cadence using Cadence ToolsToolsAshok Taneja Senior IT Architect,Cadence Design SystemsKushal Koolwall Director Strategic Alli

2、ances,Cadence Design SystemsRavi Konuru Lead Architect,Industry Solutions,IBM CloudAgenda01020304050607Electronic Design AutomationAbout Cadence Design SystemsCadence Managed Service on IBM CloudIBM-Cadence Partnership About IBM Cloud for HPCCadence Deployments On IBM CloudFuture Electronic Design A

3、utomation Electronic Design Automation One Slide OverviewOne Slide OverviewEDAEDA:Software Tools and Processes to help the total lifecycle of chip design to manufacturing.Compute:Compute:Need large Compute(5000 to 100000 vcpus or more)and multiple profiles with different CPU:Memory ratio.Storage:Sto

4、rage:typically,in Peta bytes with billions of small files spread across multiple file systems.Performance:Performance:High performance requirements on File Storage.NFS is the predominant interface.IOPS requirements can be as high as 300,000 IOPSSecurity:Security:The designs as well as the Process De

5、velopment Kit(PDK)are very high IP value and belong to different vendors.Need for very tight security.3 3rdrd party approval:party approval:Chip design environments need to be approved by Foundries before their PDKs can be used in a cloud environment.There is a security checklist that guides the app

6、rovalElectronic Design Automation Electronic Design Automation Technical ChallengesTechnical ChallengesCompute:Compute:Sustained use:Sustained use:Ability to efficiently use existing computing resources Elastic use:Elastic use:Ability to creating computing resources on demand and execute jobs when e