WITCH：用于减少高带宽存储器串扰的加权编码方案.pdf

1、WITCH:WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth Memory Seoyoon Jang*1,Sangouk Jeon*1,Kwanghyun Shin1,Dongkwon Lee1,Hankyu Chi2,Wookjin Shin2,Chanhyun Pyo2,Jaeha Kim1,Dongsuk Jeon1*(ECA)1Seoul National University,2SK hynixEmail:sangouk.jeonsnu.ac.krASP-DAC 2025Background:HBM-In

2、tegrated System Overview2Silicon InterposerBase Logic DieCore DieCore DieCore DieCore DieTSVGPU/CPU/SoCHBMPackage SubstratePHYPHYMicrobumpHigh density parallel interfaceBackground:HBM Performance Evolution3Bandwidth I/O speed Chanel density Crosstalk Next(HBM4)Bandwidth 1.5-2.5 TB/sI/O speed 10 Gbps

3、HBM3EBandwidth 1.2 TB/sI/O speed 9.6 GbpsHBM3Bandwidth 819 GB/sI/O speed 6.4 GbpsHBM2EBandwidth 461 GB/sI/O speed 3.6 GbpsHBM2Bandwidth 256 GB/sI/O speed 2.0 GbpsBackground:CrosstalkCrosstalk:Caused by capacitive and inductive couplingAggressor transits Victim affected4AggressorVictimInductive Coupl

4、ing Capacitive CouplingBackground:Crosstalk Reduction Methods XTC(Crosstalk Cancellation)Generate anti-crosstalk signals to cancel out the crosstalk Significant crosstalk reduction Large Area Overhead 100300%Area Overhead CAC(Crosstalk Avoidance Code)Using different number-based system,removing wors

5、t-case transition pattern Ex.Fibonacci Number system(FNS-based)Crosstalk minimized to a certain level&Low bit efficiency Small Area Overhead5Background:Crosstalk Level6Case ICase IICase IIIAggressorVictim0101AggressorVictim0 001AggressorVictim0110Capacitive coupling:Case I Case II Case II Case IIICr

6、osstalk LevelHighest 2CMiddle 1CLowest 0CAgg0Agg1Agg3Agg2Victim0C2C1C0C(in capacitive)Case IIICase IICase IChannel Structure7 Signal ChannelShielding Channel4 Rows.Grid Pattern:Shielding and Signal Channels Placed Alternatively Signal ChannelShielding Channel4 Rows.Channel Structure81248163264128256