SMART-GPO：门级灵敏度测量与精确估计用于毛刺功率优化.pdf

1、SMART-GPO:Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch PowerOptimizationYikang Ouyang1,Yuchao Wu1,Dongsheng Zuo1,Subhendu Roy3,Tinghuan Chen4,Zhiyao Xie2,Yuzhe Ma1Presenter:Yikang Ouyangyouyang929connect.hkust-Jan.23,20251 The Hong Kong University of Science and Technology(

2、Guangzhou)2 The Hong Kong University of Science and Technology3 Cadence Design Systems4 The Chinese University of Hong Kong,Shenzhen1Power Consumption Issue2Increasing computation of ICsCoolingReliabilityPower deliveryBattery lifeCarbon footprintImplicationsPower consumptionVLSI design is hitting“po

3、wer wall”Power becomes the key objectiveSource:Ray KurzweilGlitch Glitches are extra toggles due to the arrival time imbalances and signal toggling in the netlist.Extra dynamic power consumed3Glitch generationGlitch propagationSource:Synopsyshttps:/ Power Issues4Source:Synopsyshttps:/ up to 40%of ad

4、ditional dynamic power consumption Proportional to the number of operationsPower profiling on a BOOM chipGlitch Power Optimization:ECO Filter a propagated glitch:latch insertion Balance the input arrival time:sizing,buffering Increase the inertial delay:down-sizing,use high-Vt cells5LatchDown-sizing

5、&high-VtSizingBufferSource:Vithagan+,TCAD23Overhead:area,power,timing,more glitchK.Muthamizh Vithagan,V.Sundaresha,and J.Viraraghavan,“Geometric Programming Approach to Glitch Minimization via Gate Sizing,”IEEE TCAD,2023Related Works Geometric programming(Global)6 Heuristic search(Local)Glitch gener

6、ation and propagation Load capacitance Rank gates for opt.Glitch criticality Bathla+,TVLSI19 Power metric Wang+,SOCC11 Vithagan+,TCAD23 No guarantee on result.Any systematic framework?K.Muthamizh Vithagan,V.Sundaresha,and J.Viraraghavan,“Geometric Programming Approach to Glitch Minimization via Gate