SESSION 18 Noise-Shaping and SAR-Based ADCs.pdf

1、ISSCC 2025SESSION 18Noise-Shaping and SAR-Based ADCs18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW1 of 53 2025 IEEE International Solid-State Circuits ConferenceA Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BWHan Zhao*,Xu

2、anhao Zhang*,Qijin Deng,Jialin Hu,Zhenbing Li,Shiheng Yang,Jiaxin LiuUniversity of Electronic Science and Technology of China,Chengdu,China18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW2 of 53 2025 IEEE International Solid-State Circuits ConferenceOutline B

3、ackground Proposed fully dynamic NS SAR ADC Circuit implementations Measurement results Conclusion18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW3 of 53 2025 IEEE International Solid-State Circuits ConferenceApplication Application:Portable instrumentation I

4、mplantable devices Smart sensors Goals:High dynamic range and linearity Low static power consumption18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW4 of 53 2025 IEEE International Solid-State Circuits Conference1.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+06

5、1.E+07102030405060708090100110120P/fsnyqpJSNDR fin,hfdBISSCC 1997-2024VLSI 1997-2024FOMW=1fJ/conv-stepFOMS=185dBMotivationSNDR120dBFoMs185dBRef:B.Murmann,ADC Performance Survey 1997-2024”18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW5 of 53 2025 IEEE Intern

6、ational Solid-State Circuits ConferenceChallenge High linearity Sampling Integrator Mismatch Low power consumption Integrator power consumption Reference power consumption18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW6 of 53 2025 IEEE International Solid-St