Session 30Nonvolatile Memory and DRAM.pdf

1、Session 30 Overview:Nonvolatile Memory and DRAM MEMORY SUBCOMMI TTEECutting-edge technologies continue to emerge,leading to increased memory capacities and faster performance.Samsung demonstrates a NAND Flash memory with 4XX WL layers and 5.6Gb/s I O rate.Kioxia introduces a NAND Flash memory with t

2、he highest bit density.Samsung introduces the 1st 24Gb GDDR7 DRAM,with a 42.5Gb/s I O rate and power-efficiency techniques.Samsung presents a 16G LPDDR5X operating at 12.7Gb/s,with a self-calibrating I O scheme.SK Hynix introduces the highest-capacity(2Tb)QLC NAND Flash memory,with a six-plane archi

3、tecture.Kioxia and SK Hynix present the worlds highest density 64Gb cross-point MRAM chip.Session Chair:Seung-Jae Lee Samsung,Hwaseong,Korea Session Co-Chair:Thomas Hein Micron,Munich,Germany 502 2025 I EEE I nternational Solid-State Circuits ConferenceI SSCC 2025/SESSI ON 30/NONVOLATI LE MEMORY AND

4、 DRAM/OVERVI EW979-8-3315-4101-9/25/$31.00 2025 I EEE11:20 AM 30.4 A 16Gb 12.7Gb/s/pin LPDDR5-Ult ra-Pro DRAM wit h 4-Phase Self-Calibrat ion and AC-Coupled Transceiver Equalizat ion in a 5t h-Generat ion 10nm DRAM Process Jin-Hyeok Baek,Samsung Electronics,Hwaseong,Korea I n Paper 30.4,Samsung pres

5、ents a 16Gb 12.7Gb/s LPDDR5X DRAM with a self-calibrating I O scheme and AC-coupled equalization in a 5th-generation 10nm technology.The distributed 4-phase clock skew is reduced by 33.7%via self-calibration.11:35 AM 30.5 A 321-Layer 2Tb 4b/cell 3D-NAND-Flash Memory wit h a 75MB/s Program Throughput

6、 Wanik Cho,SK hynix,I cheon,Korea I n Paper 30.5,SK Hynix presents a 2Tb 4b/cell 3D-NAND Flash memory with a 3.2Gb/s I O speed and a 6-plane architecture.I ncreased internal-bias levels,during programming,reduce program disturbance by 18%.A precise bias generator ensures consistent bias levels acros