Session 29SRAM.pdf

1、Session 29 Overview:SRAM MEMORY SUBCOMMI TTEESRAM continues to play an indispensable role in the relentless pursuit for higher compute performance.As traditional transistor scaling slows,innovations and design-technology co-optimization(DTCO)are required more than ever to further extend SRAM s densi

2、ty,speed and functionality for energy-efficient compute.This session highlights four SRAM papers and one TCAM paper that push density,speed,power and operation boundaries by combining architectural and circuit innovations with SRAM bitcells in advanced-process technologies that include FinFET,Nanosh

3、eet and RibbonFET CMOS with backside interconnects.Session Chair:John Wuu AMD,Fort Collins,CO Session Co-Chair:Yih Wang TSMC,Hsinchu,Taiwan 490 2025 I EEE I nternational Solid-State Circuits ConferenceI SSCC 2025/SESSI ON 29/SRAM/OVERVI EW979-8-3315-4101-9/25/$31.00 2025 I EEE8:50 AM 29.3 A 3nm FinF

4、ET 2.2Gsearch/s 0.305fJ/b TCAM wit h Dynamically Gat ed Search Lines for Dat a-Cent er ASI Cs Sushil Kumar,MediaTek,San Jose,CA I n Paper 29.3,MediaTek presents a 3nm Fin-FET TCAM with dynamically-gated search lines for data center ASI Cs.The 2.2G-searches/s 0.305fJ/b design achieves a 37.7%power an

5、d a 46.6%peak-current reduction through its power-optimization features at 4.97Mb/mm2.9:15 AM 29.4 A 38Mb/mm2 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology Harold Pilo,Synopsys,Williston,VT I n Paper 29.4,Synopsys demonstrates a dual-rail SRAM design in 3nm FinFET technology.By optimizing level

6、shifters,the design achieves a 38Mb/mm2 area density,while supporting 0.38-1.4V logic and 0.54-1.4V array voltage ranges.9:30 AM 29.5 A 3nm 3.6GHz Dual-Port SRAM wit h Backend-RC Opt imizat ion and a Far-End Writ e-Assist Scheme Hidehiro Fujiwara,TSMC,Hsinchu,Taiwan I n Paper 29.5,TSMC presents a 3n