SESSION 4 Analog Techniques.pdf

1、ISSCC 2025SESSION 4Analog Techniques4.1 A 12.8 GS/s Sub-Sampling ADC Front-End with 38 GHz Input Bandwidth and 39dB SNDR for 1 to 32 GHz in 22nm FDSOI 2025 IEEE International Solid-State Circuits Conference1 of 33A 12.8GS/s Sub-Sampling ADC Front-End with 38GHz Input Bandwidth and 39dB SNDR for 1 to

2、 32GHz in 22nm FDSOIJosef Heel1,Harijot Singh Bindra1,Simon Louwsma2,Alessandro Dezzani3and Bram Nauta11University of Twente,2Teledyne DALSA,3Teledyne e2v4.1 A 12.8 GS/s Sub-Sampling ADC Front-End with 38 GHz Input Bandwidth and 39dB SNDR for 1 to 32 GHz in 22nm FDSOI 2025 IEEE International Solid-S

3、tate Circuits Conference2 of 33Outline Introduction Architecture and concept Implementation details Measurement results Conclusion4.1 A 12.8 GS/s Sub-Sampling ADC Front-End with 38 GHz Input Bandwidth and 39dB SNDR for 1 to 32 GHz in 22nm FDSOI 2025 IEEE International Solid-State Circuits Conference

4、3 of 33Introduction Increased focus on mm-wave frequencies 14Crowded RF spectrumLarger bandwidth available Higher data rates Potential of RF sampling receivers 15Enabled by advancements in ADC capability 9Flexible multi-channel/standard approaches4.1 A 12.8 GS/s Sub-Sampling ADC Front-End with 38 GH

5、z Input Bandwidth and 39dB SNDR for 1 to 32 GHz in 22nm FDSOI 2025 IEEE International Solid-State Circuits Conference4 of 33Outline Introduction Architecture and concept Implementation details Measurement results Conclusion4.1 A 12.8 GS/s Sub-Sampling ADC Front-End with 38 GHz Input Bandwidth and 39

6、dB SNDR for 1 to 32 GHz in 22nm FDSOI 2025 IEEE International Solid-State Circuits Conference5 of 33Architecture4.1 A 12.8 GS/s Sub-Sampling ADC Front-End with 38 GHz Input Bandwidth and 39dB SNDR for 1 to 32 GHz in 22nm FDSOI 2025 IEEE International Solid-State Circuits Conference6 of 33Direct samp