Session 24High-Frequency ADCs.pdf

1、Session 24 Overview:High-Frequency ADCs DATA CONVERTERS SUBCOMMITTEEDespite a long history and well-established design techniques,ADC architectures and circuit technologies f or high-speed operation continue to evolve.The conversion rates presented in this session range f rom 1 to 72GS/s,demonstrati

2、ng innovative ADC structures and circuit techniques aimed at achieving not only high speed but also exceptional energy ef ficiency.Key advancements introduced include piecewise-linear nonlinearity calibration,dual-path amplification,sub-quantizer design,a mutually exclusive selection technique to re

3、duce metastability,wideband input buf f ers,a hierarchical TI ADC in 4nm CMOS,passive gain combined with automatic buf f er power gating,and more.Session Chair:Seung-Tak Ryu KAIST,Daejeon,Korea Session Co-Chair:Vanessa Chen Carnegie Mellon University,Pittsburgh,PA 426 2025 IEEE International Solid-S

4、tate Circuits Conf erenceISSCC 2025/SESSION 24/HIGH-FREQUENCY ADCS/OVERVIEW979-8-3315-4101-9/25/$31.00 2025 IEEE8:00 AM 24.1 A 12b 3GS/s Pipelined ADC wit h Gat ed-LMS-Based Piecewise-Linear Nonlinearit y Calibrat ion Mingyang Gu,Tsinghua University,Beijing,China In Paper 24.1,Tsinghua University in

5、troduces a gated-LMS-based PWL nonlinearity calibration and dual-path amplification f or better accuracy and ef ficiency.The prototype ADC achieves 58.8dB SNDR at 3GS/s with 32.5mW power consumption,corresponding to a FoMs of 165dB.8:25 AM 24.2 A 14b 1GS/s Single-Channel Pipelined ADC wit h a Parall

6、el-Operat ion SAR Sub-Quant izer and a Dynamic-Deadzone Ring Amplifier Yue Cao,Xidian University,Xian,China In Paper 24.2,Xidian University presents a 14b 1GS/s pipelined ADC with SAR sub-quantizer,achieving 68.2dB SNDR,85.8dB SFDR,and 173.3dB FoMS.A dynamic dead-zone ring amplifier enhances ef fici