Session 17Hardware Security.pdf

1、Session 17 Overview:Hardware Security SECURI TY SUBCOMMI TTEEThe session covers hardware security solutions across design hierarchies,f rom processor architectures to circuits.The first paper introduces a sensor f or detecting side-channel eavesdropping attacks using the silicon debug tool,the laser

2、 voltage prober.The next two papers present processor architectures designed to accelerate f ully homomorphic encryption(FHE)and FHE-based cryptographic schemes.These are f ollowed by two papers that discuss physically-unclonable-f unction(PUF)circuits with extremely low error rates.The final paper

3、highlights a clock generator designed to detect f ault injection attacks.Session Chair:Takeshi Sugawara University of Electro-Communications Tokyo,JapanSession Co-Chair:Leibo Liu Tsinghua University,Beijing,China290 2025 IEEE International Solid-State Circuits Conf erenceI SSCC 2025/SESSI ON 17/HARD

4、WARE SECURI TY/OVERVI EW979-8-3315-4101-9/25/$31.00 2025 IEEE4:25 PM 17.3 A 30.4GOPS/mW MK-CKKS Processor for Secure Mult i-Part y Comput at ion Liang-Hsin Lin,National Taiwan University,Taipei,Taiwan In Paper 17.3,National Taiwan University introduces a processor f or secure multi-party computation

5、 using the multi-key(MK)CKKS scheme.The chip,f abricated using a 40nm process,reaches a maximum throughput of 6.72GOPS with 221mW power consumption at 210MHz f rom a 1.3V supply.4:50 PM 17.4 An Efficient Vt h-Tilt ing PUF Design in 3nm GAA and 8nm FinFET Technologies Bohdan Karpinskyy,Samsung Electr

6、onics,Hwaseong,Korea In Paper 17.4,Samsung describes a PUF circuit,implemented in both 3nm GAA and 8nm FinFet technologies.A Vth tilting technique f or screening of unstable selections is utilized to achieve a key error rate(KER)below 5.5E-20.5:05 PM 17.5 An Eye-Opening Arbit er PUF for Fingerprint