Session 19Frequency Synthesizers and Series-Resonance VCOs.pdf

1、Session 19 Overview:Frequency Synthesizers and Series-Resonance VCOs RF SUBCOMMITTEEFrequency synthesizers are essential components of any wireless communication systems and modern SerDes applications.The session features elven papers on ultra-low-noise fractional-N PLLs,LO systems,and series-resona

2、nce VCOs.The final paper presents a PLL with 15.8fs jitter.Session Chair:Dmytro Cherniak Infineon Technologies,Villach,Austria Session Co-Chair:Wei Deng Tsinghua University,Beijing,China 322 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 19/FREQUENCY SYNTHESIZERS AND SERIE

3、S-RESONANCE VCOS/OVERVIEW979-8-3315-4101-9/25/$31.00 2025 IEEE1:30 PM 19.1 A PVT-Robust 5.5GHz Fractional-N Cascaded RO-Based Digital PLL with Voltage-Domain Feedforward Noise Cancellation Yu Duan,University of Macau,Macau,China In Paper 19.1,the University of Macau presents a 28nm-CMOS 5.5GHz fract

4、ional-N cascaded RO-based digital PLL with voltage-domain feedforward noise cancellation achieving a 290.8fs jitter with 10%variation over PVT.1:55 PM 19.2 A 96fsrms-Jitter,-70.6dBc-Fractional-Spur Cascaded PLL Employing Two MMDs with Shared DSM for Quantization Noise Cancellation Haoming Zhang,Univ

5、ersity of Tokyo,Tokyo,Japan In Paper 19.2,the University of Tokyo presents a fractional-N cascaded PLL that uses two MMDs with a shared DSM for quantization noise cancellation.The PLL,implemented in 65nm CMOS,achieves 96fsrms jitter,a-70.6dBc worst-case fractional spur,and a-247.1dB FoM near 5.2GHz.

6、2:20 PM 19.3 A Fractional-N PLL with 34fsrms Jitter and-255.5dB FoM Based on a Multipath Feedback Technique Chao-Ching Hung,MediaTek,Hsinchu,Taiwan In Paper 19.3,MediaTek presents a 9.5GHz fractional-N PLL with a multipath feedback technique and implemented in 22nm CMOS.The PLL demonstrates 34fs jit