Session 7Ultra-High-Speed Wireline.pdf

1、Session 7 Overview:Ultra-High-Speed Wireline WIRELINE SUBCOMMITTEEThe advent of AI(artificial intelligence)and HPC(high performance computing)stretches the data communication bandwidth limit between chips,modules,and data centers,leveraging ultra-high-speed wireline transceivers.The papers in this s

2、ession describe transmitter and receiver architectures that enable ultra-high-speed operation while consuming low power.The first two papers(7.1 and 7.2)present 212.5Gb/s DSP-based PAM-4 transceivers compensating beyond long-reach channels(40dB channel loss).The third paper proposes an extra-short-r

3、each 212.5Gb/s receiver employing a slice-based CTLE and phase-interpolator-based clock generator achieving an energy efficiency of 1.11pJ/b.The fourth paper describes a 112 Gb/s DSP-based PAM-4 receiver with an LC resonator-based CTLE compensating up to 52dB channel loss.The fifth paper demonstrate

4、s a 112Gb/s discrete multitone receiver with a time-based ADC consuming 353mW.The sixth paper proposes a 106.25Gb/s PAM-4 receiver achieving an energy efficiency of 2.06pJ/b assisted by a 3-tap FFE and a 1-tap speculative DFE.Paper 7.7 and 7.9 present advancement in 50 and 60Gb/s NRZ burst-mode CDR

5、solutions,respectively,for passive optical network(PON)applications.Paper 7.8 describes a reference-less CDR exploiting a SAR-based frequency acquisition technique to achieve 63.64Gb/s/s acquisition speed.Paper 7.10,the last paper of this session demonstrates an 8-phase clock generator,achieving a w

6、ide range of clock speeds from 8 to 28GHz with the help of a dual-feedback ring oscillator.Session Chair:Be n(Hy o Gy ue m)Rhe w Samsung Ele ctroni cs,Hwase ong,Kore a Session Co-Chair:Jay Im AMD,San Jose,CA 134 2025 IEEE International Solid-State Circuits ConferenceISSCC 2025/SESSION 7/ULTRA-HIGH-S