Session 8Digital Techniques for System Adaptation, Power Management and Clocking.pdf

1、Session 8 Overview:Digital Techniques for Sy stem Adaptation,Power Management and Clocking DIGITAL CIRCUITS SUBCOMMITTEEDigital architectures continue to improve energy ef ficiency through closed-loop hardware-sof tware integration,on-die sensors,and real-time adaptation.The first f our papers in th

2、is session exemplif y power management techniques that improve computing and energy ef ficiency and enable ef ficient Dynamic Voltage and Frequency Scaling(DVFS)in computing systems such as CPUs and SoCs.In the second half of this session,papers explore advanced clocking and power management circuit

3、s,f eaturing a command-aware hybrid LDO f or HBM,a low-spur low-jitter all-digital output f requency divider,two sensors f or monitoring thermal profiles or supply and temperature simultaneously,and an on-cell battery monitoring system.Session Chair:Heein Yoon UNIST,Ulsan,South Korea Session Co-Chai

4、r:Benton Calhoun University of Virginia,Charlottesville,VA 156 2025 IEEE International Solid-State Circuits Conf erenceISSCC 2025/SESSION 8/DIGITAL TECHNIQUES FOR SYSTEM ADAPTATION,POWER MANAGEMENT AND CLOCKING979-8-3315-4101-9/25/$31.00 2025 IEEE8:00 AM 8.1 Dynamic Guard-Band Features of the IBM zN

5、ext System Tobias Webel,IBM Systems,Bblingen,Germany In Paper 8.1,IBM presents dynamic guard-band f eatures f or the 5nm 5.5GHz zNext computing system.A combination of on-die sensors,a run-time control loop,and reliability,serviceability and availability f eatures demonstrate savings of 18%total chi

6、p power corresponding to 10%system power savings enabling higher f requency,higher perf ormance,multiple system configurations and new AI f eatures.8:25 AM 8.2 Run-Time Power Management System by On-Die Power Sensor with Silicon Machine Learning-Based Calibration in a 3nm Octa-Core CPU Chien-Yu Lu,M