使用莱迪思的 FPGA 加速设计周期.pdf

1、Fast-Track Design Cycles Using Lattices FPGAsHussein OsmanMarketing DirectorLattice SemiconductorEmbedded Vision TrendsSupport multiple sensors anddisplaysMove to higher resolutions and faster frame ratesConnect MIPI and legacy componentsEnable AI processing at low powerThese trends require hardware

2、 with:Low Power Small Form Factor High Performance High Reliability Ease of Use2Lattice Semiconductor(NASDAQ:LSCC)FPGA adaptable architecture is required to accelerate compute efficientlyEdge devices typically run on battery and are thermally challenged requiring low power profileGPUs used as accele

3、rators best when executing the same instruction in parallel,also power hungryRapidly changing deep learning AI algorithmsHeterogenous compute is required with HW accelerators assisting CPUsGetting to market quicklyCompute requirement doubling every 3 month,7x faster than Moores lawSoC based heteroge

4、neous compute is rigid,the HW accelerators are not programableSpinning new versions of ASICs and ASSPs is costly limiting the update cycle of the HW blocksEdge Processing Challenges3Lattice Semiconductor(NASDAQ:LSCC)Scalable Performance To Handle Multiple Use CaseExecutes multiple use cases in paral

5、lel or serialSecureSecure device configurationHardware ProgrammableAdapts to fast changing machine learning algorithms Ultra-low Power 1 milliwatt to 5 W power consumption Flexible Computation ResourcesPre and post processing of data suchas ISP,FFT and filteringWhy FPGA for Edge AI4Lattice Semicondu

6、ctor(NASDAQ:LSCC)Hardware optimizationAlgorithmoptimizationContinuous improvement and new use cases=&AI models are rapidly evolving8070605020122021AI classificationmodel innovationThe Speed of AI Innovation Benefits Programmable Logic to Keep Delivering the Best Experience.5Lattice Semiconductor(NAS