Novel Power Optimization Methods for AIHPC Chips Workload-Aware Adaptive Voltage Scaling - Andrea Matteucci - proteanTecs.pdf

1、Andrea Matteucci,Senior Product ManagerNovel Power Optimization Methods for AI/HPC Chips:Workload-Aware Adaptive Voltage ScalingObjective highest performance(frequency),at lowest power(voltage)Performance:per requirement.Power:minimum to meet specVddmin:Minimum Operating VoltageSearch in characteriz

2、ationNot trivial:time/cost consuming,not everyone does it(fully)(We help here too)BUT VopVddmin:need to guard band for real lifeRevised:meet performance spec,at lowest power,ensuring reliabilityPerformancePowerReliabilityPerformancePowerReliabilityF cant be reduced(spec),so control VDynamic methodsD

3、VFS:SW-controlled.F,V adjusted according to application performance requirements or temperature thresholdsAVS:closed-loop method that dynamically adjusts voltage levels according to the current operating conditionsUses on-chip structures,such as PVT sensors and path emulatorsGaps:Hard:companies will

4、 pass or compromise on this to save effort,time You still cant do without those guard bands,leaving performance or power on the tableHow to Save Power?P=Pdynamic+Pleak C*Vdd2*f+Vdd*IleakHigh motivation and many approaches to semiconductor power savings Performance and power guard-bands must be taken

5、 to avoid failureGoal:tailor power to actual requirement device gets(only)what it needs,when it needs itBest practices cant avoid taking some guard-band,leaving performance/power on the tableAVS Pro tracks precise margin to failure of millions of logic paths over time and workloadsAllows voltage red

6、uction until the point of minimal timing margin(or minimum allowed voltage),while protecting from failureAvoid paying for an insurance policy until it is actually neededFrom field data:between 8%and14%power savings proteanTecs AVS ProProcess variation(Built-In)Can be zero if in H