AI-HPC - Advanced package technologies for chiplet adoption and memory integration in HPC-AI applications (1).pdf

1、OCP Global Summit October 18,2023|San Jose,CAYan Li,Jin Yang,Kam Chatterjee,Pouya Asrar,Sangnam Jeong,WooPoung Kim,SamsungAdvanced package technologies for chiplet adoption and memory integration in HPC/AI applicationsIntroduction and backgroundsAdvanced Packaging Turnkey solutionsFuture trends and

2、insightsOutline Introduction and backgroundsWhy Advanced Packaging?Moores law predicts the exponential growth of ICs since 1970s-Market needsThe exponential growth of cost per Yielded mm2 for 250 mm2 die-Challenges for Si level scaling and yieldinghttps:/ Packaging techniques are utilized to meet th

3、e market needs ChipletHeterogeneous integrationDie stackingAMD,Hot chips 2019Moores lawIntroduction and backgroundsChiplet;Heterogenous integration;die stackingM.Kang,“Heterogeneous Integration Platform for Next Generation Computing”Sixth Annual Symposium on Heterogeneous Integration,February,2023.H

4、igh yielding smaller chips and optimal process selectionModular design,design reuse and mix&matchN-1NDie stacking footprint reductionmemoryIntroduction and backgroundsTechnical and Logistic Challenges Multi-domain co-design involving both power and signal routing Thermal management Facilitate Indust

5、ry open platforms and standardizations for high-speed and low power chiplet D2D communications:Universal Chiplet Interconnect Express(UCIe),Bunch of Wires(BoW),and High Bandwidth Interconnect(HBI)etc.Establish and Clarify Agreements on Si security and responsibilities in yield,Known Good Die(KGD),pr

6、oduct or chiplet quality and reliability.Y.Kim et al,ECTC 2023Introduction and backgroundsTechnical and Logistic ChallengesRavi Mahajan,ISTFA 2021Hybrid Cu Bonding(HCB)Thermal Compressive Bonding(TCB)3D Microelectronic Packaging:From Architectures to Applications,2nd edition,Springer,2021,ISSN 1437-