29-赵彬广-FORCE-RISCV_Deployment_on_XuanTie_Cpu_Verification_Project(8).pdf

1、FORCE-RISCV Deploymenton XuanTie CPU VerificationProjectBinguang.Zhao/EthanForce-riscv Acting MaintainerWhats force-riscv？1XuanTie Deploy story2Force-riscv stage2 plan3CONTENTSWhats force-riscv？Python Frontend/C+backendPython fine grained templatesServer class cputop verificationDynamic Virtual Memo

2、ryMP scenario2020.6 Open source by FUTUREWEI.RV64G,F,D,C2022.2 v0.9/v1.0 released with RV32,paging fault,memory trait,vector 0.9 Dynamic InstructionSequencerSpike/SimulatorIntegratedRISCV RV64/32I,M,A,V2023.2 XuanTie starts stage 2 development:handcar/spike upgrade,vector 1.0,version control,mp 2023

3、.6 cmake build system ready Whats force-riscv？Provided by Futurewei:https:/ ISG:Output is ELF file can be directly loaded by env Instruction record feedback for fine-grained control Good coverage possible Hard to implementStatic ISG:Output is.s/.S file.Need toolchain Coarser granule controls bad cov

4、erage Easy to implementWhats force-riscv？Template:Command:Generated files:Gen.log:Fpix_sim.log:Whats force-riscv？Force-riscv infra:Memory ManagerVirtual Memory ManagerException:Triggers/handlersInstruction RecordsDependencyState Transition/Priviledge SwitchArch:Instructions/Registers/OperandsConfigB

5、nt ManagerReExe ManagerPhysical Page ManagerRegression systemThread Manager/Mp framework0 x50000000:ThreadSplitterSequence:split thread code0 x80000000+0 x100000 x thread_index:BootSequence:BootLoading sequence/backend0 x80011000+0 x1000000 x thread_index:EndOfTest:dead loopDynamic addresses:BranchN

6、otTaken:BranchNotTaken sequence/backendThreadSummary:ThreadSummary sequence/backend0 x80011000+0 x1000000 x thread_index:MainSequence:user sequenceDynamic address:exception handlersDynamic address:exception stackDynamic address:exception address tableupdateVMDynamic address:InitSetup sequence from b