27-The_Super_Long_RISC_V_Vector_Machine_RVSC.pdf

1、T1-The Long RISC-V Vector Machine GeneratorJiuyang LiuHUST&Chips AllianceQinjun LiPLCT/ISCASYunqian LuoTsinghua UniversityAnd other PLCT-CAAT interns and FTEsAug 25,20231/24BioJiuyang Liuliujiuyang.mesequencerGitHubPGP Key:0 x8D7B5A2/24Open Source Chip DeveloperChisel DeveloperRocketChip MaintainerC

2、hips Alliance TSC Member3/24Topic Today-T1Micro architecture show-off;Methodlogy to tune RISC-VVector performance;My 50 cents to the future ofRISC-V Vector in HPC;https:/ CoreI$D$SequencerMaskUnitPortPort PortPortVector$Coherence ManagerVRF0(dup)Next Level MemoryLSULaneLaneLaneLaneLaneLaneLaneLaneBu

3、fBufBufBufBufBufLaneXBarVRFBankedVRF(SRAM)BankedVRF(SRAM)BankedVRF(SRAM)BankedVRF(SRAM)VFUVFUVFUVFUVFUVFULongLatencyVFU(Divider)Ring Buffer(widen)To/Form SequencerCustomVFU(SoftMax,etc.)SlotFSMSlotFSMSlotFSMSlotFSM4/24The Real Vector MachineLarge DLEN with multiple VFULarge VRFSupport instruction ch

4、ainingFigure:T0 by Prof.Krste Asanovi5/24Pioneers-XiangshanCharacteristics:Dedicated vector pipeline andrename unitNo chainingShare float registers with vectorregistersDedicate VFU pipelinesShare load store unitSmall DLEN,improve code density,IFand BFU friendly.Figure:XiangShan Vector main pipeline6

5、/24Pioneers-X280Characteristics:Dedicated vector pipeline and flop basedregisters;Configurable to 512bits DLEN;Access L1D$and L2$simultaneously;Dual issue scalar core with large DLEN but onlyone lane.Figure:SiFive X280 Architecture7/24Pioneers-OthersThere are other pioneers,not listed because academ

6、ic/closed-source/no silicon products:ETH Ara:multiple lane but no chaining support,interesting toy project.UCB Hwacha:Non-standard Vector implementation,before RISC-V Vector 1.0,interestingfor decoupled vector architecture.Semidynamics Vector:multiple lane with renaming,looking forward to its custom