9.RISCV-Summit-China-2023.pdf

1、BRIDGING THE DIVIDE Unifying RISC-V through Binary TranslationDr.Philipp Tomsich Chief Technologist&Founder,VRULL GmbHRISC-V BUILDS MOMENTUMRISC-V offers the freedom for every implementer to add to,remove from,or customise the ISA as needed for their specific application or use-case.SCALES TO EVERY

2、APPLICATIONThe RISC-V ecosystem shares a common software foundation,and support the continuous innovation through custom,vendor-defined extension.INNOVATION ON A GLOBAL SCALEThe Technical Groups at RISC-V are continuously evolving the capabilities of the instruction set through new standards develop

3、ment.RAPIDLY EVOLVING CAPABILITIES2SLIDE2021State-of-the-art scalable vector extension supporting applications including ADAS,AI/ML and video processingRISC-V Vector extensionWorkloads change.RISC-V evolves.3CONTINUOUS EVOLUTIONSLIDERISC-V evolves rapidly driven by market and application requirement

4、s.RISC-V bitmanipulation extensionsInstructions that improve code-density and optimise a wide variety of workloads in general purpose computing and signal processing RISC-V scalar cryptography extensionCryptographic instructions targeting embedded workloads and microcontrollersRISC-V Hypervisor exte

5、nsionArchitectural prerequisites for virtualisation202320224SLIDESupport higher code-density with a wider range of compressed 16-bit instructionsRISC-V code-size reduction extensionsRISC-V Vector Cryptographic extensionCryptographic instructions built on the SIMD resources for high-throughput crypto

6、graphic processing in application processors and serversRISC-V Additional FP instructionsAdditional floating-point instructions motivated by real-world software workloads in image processing and scientific computingRISC-V Conditional Execution extensionInstructions to build up branchless sequences u