SESSION 21 - Audio Amplifiers.pdf

1、ISSCC 2024SESSION 21Audio Amplifiers 2024 IEEE International Solid-State Circuits Conference21.1:A 121.7dB DR and-109.0dB THD+N Filterless Digital-Input Class-D Amplifier with an HV Multibit IDAC Using Tri-level Output and Employing a Transition-Rate-Balanced Bidirectional RTDEM Scheme1 of 52A 121.7

2、dB DR and-109.0dB THD+NFilterless Digital-Input Class-D Amplifierwith an HV Multibit IDAC Using Tri-level Outputand Employing a Transition-Rate-BalancedBidirectional RTDEM SchemeHuajun Zhang*1,Mingshuang Zhang*1,Mengying Chen1,Arthur Admiraal1,Miao Zhang1,Marco Berkhout2,Qinwen Fan1*Equally Credited

3、 Authors(ECAs)1Delft University of Technology,Delft,The Netherlands2Goodix Technology,Nijmegen,The Netherlands 2024 IEEE International Solid-State Circuits Conference21.1:A 121.7dB DR and-109.0dB THD+N Filterless Digital-Input Class-D Amplifier with an HV Multibit IDAC Using Tri-level Output and Emp

4、loying a Transition-Rate-Balanced Bidirectional RTDEM Scheme2 of 52Outline Background and Prior Art Architecture Overview Implementation Measurement Results Conclusion 2024 IEEE International Solid-State Circuits Conference21.1:A 121.7dB DR and-109.0dB THD+N Filterless Digital-Input Class-D Amplifie

5、r with an HV Multibit IDAC Using Tri-level Output and Employing a Transition-Rate-Balanced Bidirectional RTDEM Scheme3 of 52Digital-Input Class-D Amplifier(CDA)Switching output stage high efficiency Digital input interface high level of integration Feedback loop suppresses output-stage distortion ID

6、AC/RDAC limits DR and THDT.Ido,ISSCC06E.Cope,ISSCC18 2024 IEEE International Solid-State Circuits Conference21.1:A 121.7dB DR and-109.0dB THD+N Filterless Digital-Input Class-D Amplifier with an HV Multibit IDAC Using Tri-level Output and Employing a Transition-Rate-Balanced Bidirectional RTDEM Sche