SESSION 28 - High-Density Power Management.pdf

1、ISSCC 2024SESSION 28High-Density Power Management28.1:A Fully Integrated,Domino-Like-Buffered Analog LDO Achieving 28dB Worst-Case Power-Supply Rejectionacross the Frequency Spectrum from 10Hz to 1GHz with 50pF On-Chip Capacitance 2024 IEEE International Solid-State Circuits Conference1 of 57A Fully

2、 Integrated,Domino-Like-Buffered Analog LDOAchieving 28dB Worst-Case Power-Supply Rejectionacross the Frequency Spectrum from 10Hz to 1GHzwith 50pF On-Chip CapacitanceJun-Gi Lee1,Hong-Hyun Bae1,Seunghyun Jang2,and Hyun-Sik Kim11 KAIST,Daejeon,Korea2 ETRI,Daejeon,Korea28.1:A Fully Integrated,Domino-L

3、ike-Buffered Analog LDO Achieving 28dB Worst-Case Power-Supply Rejectionacross the Frequency Spectrum from 10Hz to 1GHz with 50pF On-Chip Capacitance 2024 IEEE International Solid-State Circuits Conference2 of 57Outline Introduction Proposed Domino-Like-Buffered Analog LDOConventional Single-Buffere

4、d LDOProposed Domino-Like-Buffer(DLB)DesignFlipped-Voltage-Follower-based LDO with 4-stage DLBSupply-Ripple-Cancellation Technique in DLB Experimental Results Conclusion28.1:A Fully Integrated,Domino-Like-Buffered Analog LDO Achieving 28dB Worst-Case Power-Supply Rejectionacross the Frequency Spectr

5、um from 10Hz to 1GHz with 50pF On-Chip Capacitance 2024 IEEE International Solid-State Circuits Conference3 of 57Outline Introduction Proposed Domino-Like-Buffered Analog LDOConventional Single-Buffered LDOProposed Domino-Like-Buffer(DLB)DesignFlipped-Voltage-Follower-based LDO with 4-stage DLBSuppl

6、y-Ripple-Cancellation Technique in DLB Experimental Results Conclusion28.1:A Fully Integrated,Domino-Like-Buffered Analog LDO Achieving 28dB Worst-Case Power-Supply Rejectionacross the Frequency Spectrum from 10Hz to 1GHz with 50pF On-Chip Capacitance 2024 IEEE International Solid-State Circuits Con