SESSION 10 - Frequency Synthesis.pdf

1、ISSCC 2024SESSION 10Frequency Synthesis10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving Achieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4d

2、B FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference1 1 of of 4747An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and-252.4dB FoMM.Rossoni*,S.M.Dartizio*,F.Tesol

3、in,G.Castoro,R.DellOrto,C.Samori,A.L.Lacaitaand S.Levantino*Equally-Credited Authors(ECAs)Politecnico di Milano,Milan,Italy10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving A

4、chieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference2 2 of of 4747 DTC-Based Fractional-N PLLs:Motivations Prior-Art:Variable-Slope DTC Proposed Re

5、verse-Concavity Variable-Slope DTC-Adaptive Concavity Zeroing algorithm Implementation and Measurements Conclusions Outline10.110.1:An An 8.758.75GHz FractionalGHz Fractional-N Digital PLL with a ReverseN Digital PLL with a Reverse-Concavity VariableConcavity Variable-Slope DTC Slope DTC Achieving A

6、chieving 57.357.3fsrms Integrated Jitter and fsrms Integrated Jitter and-252.4252.4dB FoMdB FoM 2024 2024 IEEE IEEE International SolidInternational Solid-State Circuits ConferenceState Circuits Conference3 3 of of 4747 DTC-Based Fractional-N PLLs:Motivations Prior-Art:Variable-Slope DTC Proposed Re