SESSION 13 - High-Density Memory and Interfaces.pdf

1、ISSCC 2024SESSION 13High-Density Memory and Interfaces13.1 A 35.4-Gb/s/pin 16-Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry 2024 IEEE International Solid-State Circuits Conference1 of 34A 35.4-Gb/s/pin 16-Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO CircuitryJa

2、ehyeok Yang,Hyeongjun Ko,Kyunghoon Kim,Hyunsu Park,Jihwan Park,Ji-Hyo Kang,Jinyoup Cha,Seongjin Kim,Youngtaek Kim,Minsoo Park,Gangsik Lee,Keonho Lee,Sanghoon Lee,Gyunam Jeon,Sera Jeong,Yongsuk Joo,Jaehoon Cha,Seonwoo Hwang,Boram Kim,Sangyeon Byeon,Sungkwon Lee,Hyeonyeol Park,Joohwan Cho,Jonghwan Kim

3、SK Hynix13.1 A 35.4-Gb/s/pin 16-Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry 2024 IEEE International Solid-State Circuits Conference2 of 34Outline Industry Trends&Issues GDDR7 Overall ArchitectureMajor Changes&Placement Clocking Architecture TX Implementation RX Implementati

4、on Measurement Results Conclusions13.1 A 35.4-Gb/s/pin 16-Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry 2024 IEEE International Solid-State Circuits Conference3 of 34Outline Industry Trends&Issues GDDR7 Overall ArchitectureMajor Changes&Placement Clocking Architecture TX Impl

5、ementation RX Implementation Measurement Results Conclusions13.1 A 35.4-Gb/s/pin 16-Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry 2024 IEEE International Solid-State Circuits Conference4 of 34This Work0610141822268162432Published YearSpeed Gb/s/pin40ISSCC18ISSCC18ISSCC17ISSCC

6、16ISSCC11ISSCC09ISSCC08ISSCC07ISSCC06ISSCC21ISSCC21ISSCC22GDDR3GDDR4GDDR5(X)GDDR6(X)GDDR7NRZPAM3Trend of Graphics Memory13.1 A 35.4-Gb/s/pin 16-Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry 2024 IEEE International Solid-State Circuits Conference5 of 34IDD3NIDD0IDD4RIDD4WIDD2N